| |
| 2007 | ||
|---|---|---|
| 2 | EE | Régis Roubadia, Sami Ajram, Guy Cathébras: Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology. ISCAS 2007: 2490-2493 |
| 2006 | ||
| 1 | EE | Régis Roubadia, Sami Ajram, Guy Cathébras: Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. PATMOS 2006: 458-467 |
| 1 | Sami Ajram | [1] [2] |
| 2 | Guy Cathébras | [1] [2] |