| 2008 |
|---|
| 5 | EE | B. Chung,
J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application.
Integration 41(1): 9-16 (2008) |
| 2006 |
|---|
| 4 | EE | B. Chung,
J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.
ISCAS 2006 |
| 3 | EE | B. Chung,
J. B. Kuo:
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.
PATMOS 2006: 237-246 |
| 2005 |
|---|
| 2 | EE | G. Y. Liu,
N. C. Wang,
J. B. Kuo:
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications.
ISCAS (5) 2005: 5258-5261 |
| 2002 |
|---|
| 1 | EE | E. Shen,
J. B. Kuo:
0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.
ISCAS (4) 2002: 583-586 |
