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Gregorio Cappuccino

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2008
9EEAndrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo: Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. PATMOS 2008: 318-327
2007
8EEAndrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo: Settling Time Minimization of Operational Amplifiers. PATMOS 2007: 107-116
2006
7EEAndrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo: A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. PATMOS 2006: 311-318
6EEAndrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo: Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. PATMOS 2006: 524-531
2005
5EEGregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo: Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. PATMOS 2005: 329-336
2003
4EEGregorio Cappuccino: Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. DSD 2003: 138-143
2002
3EEGregorio Cappuccino, Giuseppe Cocorullo: Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. PATMOS 2002: 438-447
2001
2EEGregorio Cappuccino, Giuseppe Cocorullo: CMOS sizing rule for high performance long interconnects. DATE 2001: 817
1999
1EEGregorio Cappuccino, Giuseppe Cocorullo: A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. EUROMICRO 1999: 1204-1208

Coauthor Index

1Francesco A. Amoroso [9]
2Giuseppe Cocorullo [1] [2] [3] [5] [6] [7] [8] [9]
3Andrea Pugliese [5] [6] [7] [8] [9]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)