| 2008 |
|---|
| 3 | EE | B. Chung,
J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application.
Integration 41(1): 9-16 (2008) |
| 2006 |
|---|
| 2 | EE | B. Chung,
J. B. Kuo:
Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.
ISCAS 2006 |
| 1 | EE | B. Chung,
J. B. Kuo:
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.
PATMOS 2006: 237-246 |
