| 2006 |
|---|
| 5 | EE | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.
DSD 2006: 423-432 |
| 4 | EE | Guadalupe Miñana,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
José Manuel Colmenar:
A Power-Aware Technique for Functional Units in High-Performance Processors.
DSD 2006: 456-459 |
| 3 | EE | José Manuel Colmenar,
Oscar Garnica,
Juan Lanchares,
José Ignacio Hidalgo,
Guadalupe Miñana,
Sonia López:
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.
Euro-Par 2006: 495-505 |
| 2 | EE | Guadalupe Miñana,
José Ignacio Hidalgo,
Oscar Garnica,
Juan Lanchares,
José Manuel Colmenar,
Sonia López:
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.
PATMOS 2006: 514-523 |
| 2005 |
|---|
| 1 | EE | Guadalupe Miñana,
Oscar Garnica,
José Ignacio Hidalgo,
Juan Lanchares,
José Manuel Colmenar:
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.
PATMOS 2005: 40-48 |
