| 2008 |
|---|
| 8 | EE | Fahd Ben Abdeljelil,
Benjamin Nicolle,
William Tatinian,
Lorenzo Carpineto,
Jean Oudinot,
Gilles Jacquemod:
Application of Bottom-Up Methodology to RTW VCO.
ISVLSI 2008: 46-50 |
| 2006 |
|---|
| 7 | EE | Benjamin Nicolle,
William Tatinian,
Jean Oudinot,
Gilles Jacquemod:
Hierarchical Modeling of a Fractional Phase Locked Loop.
PATMOS 2006: 450-457 |
| 6 | EE | Jean Oudinot:
Top Verification of Low Power System with "Checkerboard" Approach.
PATMOS 2006: 672 |
| 2004 |
|---|
| 5 | EE | B. Hecker,
M. Chavassieux,
M. Laflutte,
E. Beguin,
L. Lagasse,
Jean Oudinot:
VHDL-AMS Library Development for Pacemaker Applications.
DATE 2004: 338-341 |
| 4 | EE | Patricia Desgreys,
Yannick Hervé,
Jean Oudinot,
S. Snaidero,
Mohamed Karray:
SoC modelling for virtual prototyping with VHDL-AMS.
FDL 2004: 168-180 |
| 2003 |
|---|
| 3 | EE | Jean Oudinot,
G. Overton,
Aitor Endemaño Isasi,
Marc P. Y. Desmulliez,
Jean-Yves Fourniols,
Sylvaine Muratet:
Micromotor Simulation with VHDL-AMS.
FDL 2003: 185-197 |
| 2 | EE | Jean Oudinot:
The Most Complete Mixed-Signal Simulation Solution with ADVance MS.
PATMOS 2003: 193 |
| 2002 |
|---|
| 1 | | Jean Oudinot,
Serge Scotti,
Jean Ravatin,
Audrey Le-clercq,
Jacky Lebrun:
Full Transceiver Circuit Simulation using VHDL-AMS.
ESM 2002: 642-652 |
