| 2008 |
|---|
| 9 | EE | Jiayi Liu,
Sheqin Dong,
Xianlong Hong,
Yibo Wang,
Ou He,
Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
ASP-DAC 2008: 772-775 |
| 8 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong:
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.
ISVLSI 2008: 221-226 |
| 2007 |
|---|
| 7 | EE | Yibo Wang,
Jun Li:
Is your IP address prefix well-served by internet routing?
CoNEXT 2007: 69 |
| 6 | EE | Jun Li,
Dejing Dou,
Shiwoong Kim,
Han Qin,
Yibo Wang:
On Knowledge-Based Classification of Abnormal BGP Events.
ICISS 2007: 267-271 |
| 5 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong,
Yi Zou:
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.
IEICE Transactions 90-A(5): 1028-1037 (2007) |
| 2006 |
|---|
| 4 | EE | Lijuan Luo,
Qiang Zhou,
Yici Cai,
Xianlong Hong,
Yibo Wang:
A novel technique integrating buffer insertion into timing driven placement.
ISCAS 2006 |
| 3 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong:
Performance and power aware buffered tree construction.
ISCAS 2006 |
| 2005 |
|---|
| 2 | EE | Yici Cai,
Yibo Wang,
Xianlong Hong:
A global interconnect optimization algorithm under accurate delay model using solution space smoothing.
ISCAS (1) 2005: 93-96 |
| 1 | EE | Yibo Wang,
Yici Cai,
Xianlong Hong:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.
VLSI Design 2005: 91-96 |
