Yibo Wang

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9EEJiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto: Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775
8EEYibo Wang, Yici Cai, Xianlong Hong: A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226
7EEYibo Wang, Jun Li: Is your IP address prefix well-served by internet routing? CoNEXT 2007: 69
6EEJun Li, Dejing Dou, Shiwoong Kim, Han Qin, Yibo Wang: On Knowledge-Based Classification of Abnormal BGP Events. ICISS 2007: 267-271
5EEYibo Wang, Yici Cai, Xianlong Hong, Yi Zou: Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Transactions 90-A(5): 1028-1037 (2007)
4EELijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang: A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006
3EEYibo Wang, Yici Cai, Xianlong Hong: Performance and power aware buffered tree construction. ISCAS 2006
2EEYici Cai, Yibo Wang, Xianlong Hong: A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) 2005: 93-96
1EEYibo Wang, Yici Cai, Xianlong Hong: A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design 2005: 91-96

Coauthor Index

1Yici Cai [1] [2] [3] [4] [5] [8]
2Sheqin Dong [9]
3Dejing Dou [6]
4Satoshi Goto [9]
5Ou He [9]
6Xianlong Hong [1] [2] [3] [4] [5] [8] [9]
7Shiwoong Kim [6]
8Jun Li [6] [7]
9Jiayi Liu [9]
10Lijuan Luo [4]
11Han Qin [6]
12Qiang Zhou [4]
13Yi Zou [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)