| 2008 |
|---|
| 10 | EE | Grzegorz Pastuszak:
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection.
ISVLSI 2008: 203-208 |
| 9 | EE | Grzegorz Pastuszak:
A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC.
IEEE Trans. Circuits Syst. Video Techn. 18(7): 949-960 (2008) |
| 2006 |
|---|
| 8 | | Grzegorz Pastuszak:
Architecture Design for the Context Formatter in the H.264/AVC Encoder.
DDECS 2006: 71-72 |
| 7 | EE | Grzegorz Pastuszak:
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding.
PARELEC 2006: 380-385 |
| 2005 |
|---|
| 6 | EE | Grzegorz Pastuszak:
Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder.
ICIAP 2005: 604-611 |
| 5 | EE | Grzegorz Pastuszak:
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000.
ICME 2005: 225-228 |
| 4 | EE | Grzegorz Pastuszak:
A high-performance architecture for embedded block coding in JPEG 2000.
IEEE Trans. Circuits Syst. Video Techn. 15(9): 1182-1191 (2005) |
| 2004 |
|---|
| 3 | | Grzegorz Pastuszak:
Hardware-Oriented Analysis of the Arithmetic Coding - Comparative Study of JPEG2000 and H.264/AVC Compression Standards.
ICETE (3) 2004: 309-316 |
| 2 | | Grzegorz Pastuszak:
A high-performance architecture of arithmetic coder in JPEG2000.
ICME 2004: 1431-1434 |
| 1 | EE | Grzegorz Pastuszak:
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding.
PARELEC 2004: 303-308 |
