| |
| 2008 | ||
|---|---|---|
| 8 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: FSMD partitioning for low power using simulated annealing. ISCAS 2008: 1244-1247 |
| 7 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: FSMD Partitioning for Low Power Using ILP. ISVLSI 2008: 63-68 |
| 2007 | ||
| 6 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: Towards Automated Power Gating of Registers using CoDeL. ISCAS 2007: 1629-1632 |
| 5 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. ISVLSI 2007: 508-509 |
| 4 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. SAMOS 2007: 294-303 |
| 2006 | ||
| 3 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: Power efficient rapid hardware development using CoDel and automated clock gating. ISCAS 2006 |
| 2 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: Efficient Automated Clock Gating Using CoDeL. SAMOS 2006: 79-88 |
| 2004 | ||
| 1 | EE | Nainesh Agarwal, Nikitas J. Dimopoulos: Using CoDeL to Rapidly Prototype Network Processsor Extensions. SAMOS 2004: 333-342 |
| 1 | Nikitas J. Dimopoulos | [1] [2] [3] [4] [5] [6] [7] [8] |