| 2009 |
|---|
| 14 | EE | Kazuteru Namba,
Yoshikazu Matsui,
Hideo Ito:
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.
J. Electronic Testing 25(1): 97-105 (2009) |
| 2008 |
|---|
| 13 | EE | Shuangyu Ruan,
Kazuteru Namba,
Hideo Ito:
Soft Error Hardened FF Capable of Detecting Wide Error Pulse.
DFT 2008: 272-280 |
| 12 | EE | Kazuteru Namba,
Hideo Ito:
Delay Fault Testability on Two-Rail Logic Circuits.
DFT 2008: 482-490 |
| 11 | EE | Yoichi Sasaki,
Kazuteru Namba,
Hideo Ito:
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.
J. Electronic Testing 24(1-3): 11-19 (2008) |
| 2007 |
|---|
| 10 | EE | Takashi Ikeda,
Kazuteru Namba,
Hideo Ito:
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.
DFT 2007: 282-290 |
| 9 | EE | Kazuteru Namba,
Eiji Fujiwara:
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings.
Systems and Computers in Japan 38(8): 54-60 (2007) |
| 2006 |
|---|
| 8 | EE | Yoichi Sasaki,
Kazuteru Namba,
Hideo Ito:
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.
DFT 2006: 327-335 |
| 7 | EE | Kazuteru Namba,
Hideo Ito:
Proposal of Testable Multi-Context FPGA Architecture.
IEICE Transactions 89-D(5): 1687-1693 (2006) |
| 6 | EE | Kazuteru Namba,
Hideo Ito:
Redundant Design for Wallace Multiplier.
IEICE Transactions 89-D(9): 2512-2524 (2006) |
| 2005 |
|---|
| 5 | EE | Kazuteru Namba,
Hideo Ito:
Design of Defect Tolerant Wallace Multiplier.
PRDC 2005: 300-304 |
| 4 | EE | Kazuteru Namba,
Hideo Ito:
Scan Design for Two-Pattern Test without Extra Latches.
IEICE Transactions 88-D(12): 2777-2785 (2005) |
| 3 | EE | Kazuteru Namba,
Hideo Ito:
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation.
IEICE Transactions 88-D(9): 2135-2142 (2005) |
| 2001 |
|---|
| 2 | EE | Kazuteru Namba,
Eiji Fujiwara:
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.
DFT 2001: 299-307 |
| 1 | EE | Kazuteru Namba,
Eiji Fujiwara:
A class of systematic m-ary single-symbol error correcting codes.
Systems and Computers in Japan 32(6): 21-28 (2001) |
