| 2008 |
|---|
| 11 | EE | Tadayoshi Horita,
Yuuji Katou,
Itsuo Takanami:
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches.
IEICE Transactions 91-A(2): 623-632 (2008) |
| 10 | EE | Tadayoshi Horita,
Itsuo Takanami,
Masatoshi Mori:
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
IEICE Transactions 91-D(4): 1168-1175 (2008) |
| 2006 |
|---|
| 9 | EE | Tadayoshi Horita,
Takurou Murata,
Itsuo Takanami:
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.
DFT 2006: 554-562 |
| 2001 |
|---|
| 8 | EE | Tadayoshi Horita,
Itsuo Takanami:
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.
PRDC 2001: 233-240 |
| 2000 |
|---|
| 7 | EE | Tadayoshi Horita,
Itsuo Takanami:
A System for Efficiently Self-Reconstructing E-1 1 \over 2 -Track Switch Torus Arrays.
ISPAN 2000: 44-49 |
| 6 | | Tadayoshi Horita,
Itsuo Takanami:
A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.
PDPTA 2000 |
| 5 | EE | Tadayoshi Horita,
Itsuo Takanami:
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.
IEEE Trans. Computers 49(6): 542-552 (2000) |
| 1999 |
|---|
| 4 | EE | Tadayoshi Horita,
Itsuo Takanami:
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.
ISPAN 1999: 135-137 |
| 1997 |
|---|
| 3 | EE | Itsuo Takanami,
Tadayoshi Horita:
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.
DFT 1997: 218-226 |
| 2 | EE | Tadayoshi Horita,
Itsuo Takanami:
A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.
ISPAN 1997: 16-22 |
| 1 | EE | Itsuo Takanami,
Tadayoshi Horita:
A built-in self-reconfigurable scheme for 3D mesh arrays.
ISPAN 1997: 458-464 |
