| |
| 2007 | ||
|---|---|---|
| 2 | EE | Sanghoan Chang, Gwan Choi: Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. VLSI Design 2007: 109-114 |
| 2006 | ||
| 1 | EE | Sanghoan Chang, Gwan Choi: Timing Failure Analysis of Commercial CPUs Under Operating Stress. DFT 2006: 245-253 |
| 1 | Gwan S. Choi (Gwan Choi) | [1] [2] |