Ondrej Novák

2007
15		Jiri Jenícek, Ondrej Novák: Test Pattern Compression Based on Pattern Overlapping. DDECS 2007: 29-34
2006
14		Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 IEEE Computer Society 2006
13		Martin Stáva, Ondrej Novák: HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. DDECS 2006: 250-252
12		Leos Kafka, Ondrej Novák: FPGA-based Fault Simulator. DDECS 2006: 274-278
11	EE	Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský: Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. DFT 2006: 300-308
10	EE	Martin Stáva, Ondrej Novák: Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. DSD 2006: 251-256
9	EE	Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar: Conference Reports. IEEE Design & Test of Computers 23(4): 262-265 (2006)
2005
8	EE	Ondrej Novák, Jirí Zahrádka, Zdenek Plíva: COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits. EDCC 2005: 403-414
2004
7	EE	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa: Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electronic Testing 20(1): 109-122 (2004)
2003
6	EE	Ondrej Novák: Comparison of Test Pattern Decompression Techniques. DATE 2003: 11182-11183
2001
5	EE	Ondrej Novák, Jiri Nosek: Test Pattern Decompression Using a Scan Chain. DFT 2001: 110-115
4	EE	Ondrej Novák, Jiri Nosek: Test-per-Clock Testing of the Circuits with Scan. IOLTW 2001: 90-
2000
3	EE	Ondrej Novák, Jiri Nosek: On Using Deterministic Test Sets in BIST. IOLTW 2000: 127-132
1999
2	EE	Ondrej Novák: Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata. EDCC 1999: 303-320
1988
1		P. Golan, Ondrej Novák, Jan Hlavicka: Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. IEEE Trans. Computers 37(4): 496-500 (1988)

Coauthor Index

1	Bashir M. Al-Hashimi	[9]
2	Jiri Bucek	[14]
3	Tomasz Garbolino	[7]
4	P. Golan	[1]
5	Krzysztof Gucwa	[7]
6	Jan Hlavicka	[1]
7	Andrzej Hlawiczka	[7]
8	Michal Jarkovský	[11]
9	Jiri Jenícek	[11] [15]
10	Leos Kafka	[12]
11	Zdenek Kotásek	[14]
12	Pavel Kubalík	[14]
13	Hana Kubatova	[9] [14]
14	Zbynek Mader	[11]
15	Erik Jan Marinissen	[9]
16	Jiri Nosek	[3] [4] [5] [7]
17	Zdenek Plíva	[7] [8] [11]
18	C. P. Ravikumar	[9]
19	Matteo Sonza Reorda	[14]
20	Martin Stáva	[10] [13]
21	Bernd Straube	[14]
22	Mitra Subhasish	[9]
23	Raimund Ubar	[14]
24	Jirí Zahrádka	[8]

Colors in the list of coauthors