2009 | ||
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27 | EE | Luca Sterpone: Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. ARC 2009: 85-96 |
2008 | ||
26 | EE | Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, Luca Sterpone: Differential gene expression graphs: A data structure for classification in DNA microarrays. BIBE 2008: 1-6 |
25 | EE | Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, Luca Sterpone: A graph-based representation of Gene Expression profiles in DNA microarrays. CIBCB 2008: 75-82 |
24 | EE | Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, H. Guzman-Miranda: On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications. DATE 2008: 336-341 |
23 | EE | Luca Sterpone: FPGA PAL Design Tools. Wiley Encyclopedia of Computer Science and Engineering 2008 |
22 | EE | Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante: Software and Hardware Techniques for SEU Detection in IP Processors. J. Electronic Testing 24(1-3): 35-44 (2008) |
2007 | ||
21 | EE | Luca Sterpone, Massimo Violante: A new decompression system for the configuration process of SRAM-based FPGAS. ACM Great Lakes Symposium on VLSI 2007: 241-246 |
20 | EE | Luca Sterpone, Massimo Violante: A new hardware architecture for performing the gridding of DNA microarray images. ACM Great Lakes Symposium on VLSI 2007: 341-346 |
19 | Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego: An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. DDECS 2007: 261-266 | |
18 | EE | Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante: Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. DFT 2007: 79-86 |
17 | EE | Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT 2007: 96-104 |
16 | EE | Luca Sterpone, Massimo Violante: Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. European Test Symposium 2007: 159-164 |
15 | EE | Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196 |
14 | EE | Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda: On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs CoRR abs/0710.4688: (2007) |
13 | EE | Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro: Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electronic Testing 23(1): 47-54 (2007) |
2006 | ||
12 | EE | Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante: A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51 |
11 | Luca Sterpone, Massimo Violante: ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. DDECS 2006: 54-58 | |
10 | EE | Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. DFT 2006: 265-273 |
9 | EE | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82 |
8 | EE | Luca Sterpone, Massimo Violante: Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. IOLTS 2006: 189-190 |
7 | EE | Luca Sterpone, Massimo Violante: A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. IEEE Trans. Computers 55(6): 732-744 (2006) |
6 | EE | Luca Sterpone, Massimo Violante: Hardening FPGA-based Systems Against SEUs: A New Design Methodology. JCP 1(1): 22-30 (2006) |
2005 | ||
5 | EE | Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda: On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. DATE 2005: 1290-1295 |
4 | EE | Luca Sterpone, Massimo Violante: A design flow for protecting FPGA-based systems against single event upsets. DFT 2005: 436-444 |
3 | EE | Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante: New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO 2005: 2193-2194 |
2 | EE | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS 2005: 54-59 |
2004 | ||
1 | EE | Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS 2004: 115-120 |