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G. Fraidy Bouesse

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2007
6EEG. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on quasi delay insensitive asynchronous circuits: formalization and improvement CoRR abs/0710.3443: (2007)
2006
5EEG. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES 2006: 384-398
2005
4EEG. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE 2005: 424-429
3EEG. Fraidy Bouesse, Marc Renaudin, Gilles Sicard: Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC 2005: 11-24
2004
2EEMarc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain: High Security Smartcards. DATE 2004: 228-233
2003
1EEPhilippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191

Coauthor Index

1Sophie Dumont [4] [6]
2Fabien Germain [2] [4] [6]
3Philippe Maurine [1]
4Ph. Proust [2]
5Marc Renaudin [1] [2] [3] [4] [5] [6]
6Jean-Baptiste Rigaud [1]
7Gilles Sicard [1] [3] [5]
8Laurent Sourgen [2]
9J. P. Tual [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)