Integration, Volume 24

Volume 24, Number 1, December 1997

Mohammed A. Aloqeely, Mohammed A. Al-Turaigi, Saleh A. Alshebeili:
A new approach for the design of linear systolic arrays for computing third-order cumulants. 1-17
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Vida Vakilotojar, Peter A. Beerel:
RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking. 19-35
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Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac:
A non-iterative gate resizing algorithm for high reduction in power consumption. 37-52
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Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida:
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. 53-77
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An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin:
VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. 79-97
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Shihming Liu, Massoud Pedram, Alvin M. Despain:
State assignment based on two-dimensional placement and hypercube mapping. 101-118
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Guy Even, Ami Litman:
Overcoming chip-to-chip delays and clock skews. 119-133
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Y. P. Chen, D. F. Wong:
On retiming for FPGA logic module minimization. 135-145
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Y. P. Chen, D. F. Wong:
A graph theoretic approach to feed-through pin assignment. 147-158
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Aravind R. Valkodai, Tajinder Manku:
Modeling and designing silicon thin-film inductors and transformers using HSPICE for RFIC applications. 159-171
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