2007 |
21 | EE | Themistoklis Haniotakis,
Y. Tsiatouhas,
Dimitris Nikolos,
Costas Efstathiou:
Testable Designs of Multiple Precharged Domino Circuits.
IEEE Trans. VLSI Syst. 15(4): 461-465 (2007) |
2006 |
20 | EE | Haridimos T. Vergos,
Costas Efstathiou:
Novel Modulo 2n + 1 Multipliers.
DSD 2006: 168-175 |
2005 |
19 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Giorgos Dimitrakopoulos,
Dimitris Nikolos:
Efficient Diminished-1 Modulo 2^n+1 Multipliers.
IEEE Trans. Computers 54(4): 491-496 (2005) |
18 | EE | Haridimos T. Vergos,
Costas Efstathiou:
On the Design of Efficient Modular Adders.
Journal of Circuits, Systems, and Computers 14(5): 965-972 (2005) |
2004 |
17 | EE | Haridimos T. Vergos,
Costas Efstathiou:
Diminished-1 Modulo 2n + 1 Squarer Design.
DSD 2004: 380-386 |
16 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Dimitris Nikolos:
Modified Booth Modulo 2n-1 Multipliers.
IEEE Trans. Computers 53(3): 370-374 (2004) |
15 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Dimitris Nikolos:
Fast Parallel-Prefix Modulo 2^n+1 Adders.
IEEE Trans. Computers 53(9): 1211-1216 (2004) |
2003 |
14 | EE | Giorgos Dimitrakopoulos,
Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
A Family of Parallel-Pre.x Modulo 2n - 1 Adders.
ASAP 2003: 326-336 |
13 | EE | D. G. Nikolos,
Dimitris Nikolos,
Haridimos T. Vergos,
Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders.
IOLTS 2003: 89-93 |
12 | EE | Giorgos Dimitrakopoulos,
Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders.
ISCAS (5) 2003: 225-228 |
11 | EE | D. G. Nikolos,
Dimitris Nikolos,
Haridimos T. Vergos,
Costas Efstathiou:
Efficient BIST schemes for RNS datapaths.
ISCAS (5) 2003: 573-576 |
10 | EE | K. Katzourakis,
George Kormentzas,
Kimon P. Kontovasilis,
Costas Efstathiou:
A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks.
MMNS 2003: 259-271 |
9 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Dimitris Nikolos:
Modulo 2n±1 Adder Design Using Select-Prefix Blocks.
IEEE Trans. Computers 52(11): 1399-1406 (2003) |
8 | EE | Haridimos T. Vergos,
Dimitris Nikolos,
Maciej Bellos,
Costas Efstathiou:
Deterministic BIST for RNS Adders.
IEEE Trans. Computers 52(7): 896-906 (2003) |
2002 |
7 | EE | Haridimos T. Vergos,
Costas Efstathiou,
Dimitris Nikolos:
Diminished-One Modulo 2n+1 Adder Design.
IEEE Trans. Computers 51(12): 1389-1399 (2002) |
2001 |
6 | EE | Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.
IEEE Symposium on Computer Arithmetic 2001: 211-217 |
5 | EE | Y. Tsiatouhas,
Th. Haniotakis,
Dimitris Nikolos,
Costas Efstathiou:
Concurrent Detection of Soft Errors Based on Current Monitoring.
IOLTW 2001: 106-110 |
2000 |
4 | EE | Th. Haniotakis,
Y. Tsiatouhas,
Dimitris Nikolos,
Costas Efstathiou:
On Testability of Multiple Precharged Domino Logic.
ISQED 2000: 299-304 |
3 | EE | Lampros Kalampoukas,
Dimitris Nikolos,
Costas Efstathiou,
Haridimos T. Vergos,
John Kalamatianos:
High-Speed Parallel-Prefix Modulo 2n-1 Adders.
IEEE Trans. Computers 49(7): 673-680 (2000) |
1990 |
2 | | Antonis M. Paschalis,
Costas Efstathiou,
Constantine Halatsis:
An Efficient TSC 1-out-of-3 Code Checker.
IEEE Trans. Computers 39(3): 407-411 (1990) |
1984 |
1 | | Costas Efstathiou,
Constantine Halatsis:
Modular design of totally self-checking checkers for 1-out-of-n codes.
Fehlertolerierende Rechensysteme 1984: 164-176 |