| 2006 |
|---|
| 5 | EE | Artur Balasinski:
Question: DRC or DfM ? Answer: FMEA and ROI.
ISQED 2006: 789-794 |
| 2005 |
|---|
| 4 | EE | Krzysztof Iniewski,
Valery Axelrad,
Andrei Shibkov,
Artur Balasinski,
Sebastian Magierowski,
Rafal Dlugosz,
A. Dabrowski:
3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection.
ISCAS (2) 2005: 1154-1157 |
| 3 | EE | Artur Balasinski:
DfM for SoC, invited.
IWSOC 2005: 41-46 |
| 2004 |
|---|
| 2 | EE | Krzysztof Iniewski,
Valery Axelrad,
Andrei Shibkov,
Artur Balasinski,
Marek Syrzycki:
Design Strategies for ESD Protection in SOC.
IWSOC 2004: 210-214 |
| 2000 |
|---|
| 1 | EE | Valery Axelrad,
Nicolas B. Cobb,
M. O'Brien,
Thuy Do,
Tom Donnelly,
Yuri Granik,
Emile Y. Sahouria,
Victor Boksha,
Artur Balasinski:
Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs.
ISQED 2000: 461-466 |
