| 2006 |
|---|
| 8 | EE | Jia Di,
Jiann S. Yuan,
Ronald F. DeMara:
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integration 39(2): 90-112 (2006) |
| 7 | EE | Jia Di,
Jiann S. Yuan:
Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design.
J. Low Power Electronics 2(2): 201-216 (2006) |
| 2005 |
|---|
| 6 | | Jiann S. Yuan,
Jia Di:
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers.
CDES 2005: 218-223 |
| 2004 |
|---|
| 5 | EE | Scott C. Smith,
Ronald F. DeMara,
Jiann S. Yuan,
D. Ferguson,
D. Lamb:
Optimization of NULL convention self-timed circuits.
Integration 37(3): 135-165 (2004) |
| 2003 |
|---|
| 4 | EE | Jia Di,
Jiann S. Yuan:
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.
ACM Great Lakes Symposium on VLSI 2003: 64-67 |
| 3 | EE | Jia Di,
Jiann S. Yuan,
Ronald F. DeMara:
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
ISVLSI 2003: 260-261 |
| 2001 |
|---|
| 2 | EE | Scott C. Smith,
Ronald F. DeMara,
Jiann S. Yuan,
M. Hagedorn,
D. Ferguson:
Delay-insensitive gate-level pipelining.
Integration 30(2): 103-131 (2001) |
| 2000 |
|---|
| 1 | EE | Jiann S. Yuan:
Overview of SiGe Technology Modeling and Application.
ISQED 2000: 67-72 |
