| 2008 |
|---|
| 8 | EE | Zhihong Liu,
Jianfeng Ma,
Qiping Huang,
Sang-Jae Moon:
A pairwise key establishment scheme for heterogeneous sensor networks.
HeterSanet 2008: 53-60 |
| 7 | EE | Zhihong Liu,
Jianfeng Ma,
Qiping Huang,
Sang-Jae Moon:
Keying material based key pre-distribution scheme.
ISI 2008: 218-221 |
| 6 | | Zhihong Liu,
Jianfeng Ma,
Qiping Huang,
Sang-Jae Moon:
Keying Material Based Key Pre-distribution Scheme for Sensor Networks.
Ad Hoc & Sensor Wireless Networks 6(1-2): 67-89 (2008) |
| 2007 |
|---|
| 5 | EE | Ning Gu,
Zhihong Liu,
Tun Lu,
Fang Wang:
Fuzzy Classification for Manufacture Design Documents Based on Domain Ontology and Document Structure Tagging.
CSCWD 2007: 629-634 |
| 2006 |
|---|
| 4 | EE | Zhihong Liu,
Bruce McGaughy,
James Z. Ma:
Design tools for reliability analysis.
DAC 2006: 182-187 |
| 2001 |
|---|
| 3 | | Lifeng Wu,
Zhihong Liu:
Full-Chip Reliability Simulation for VDSM Integrated Circuits.
Microelectronics Reliability 41(9-10): 1273-1278 (2001) |
| 2000 |
|---|
| 2 | EE | Yoshiyuki Kawakami,
Jingkun Fang,
Hirokazu Yonezawa,
Nobufusa Iwanishi,
Lifeng Wu,
Alvin I-Hsien Chen,
Norio Koike,
Ping Chen,
Chune-Sin Yeh,
Zhihong Liu:
Gate-level aged timing simulation methodology for hot-carrier reliability assurance.
ASP-DAC 2000: 289-294 |
| 1 | EE | Lifeng Wu,
Jingkun Fang,
Heting Yan,
Ping Chen,
Alvin I-Hsien Chen,
Yoshifumi Okamoto,
Chune-Sin Yeh,
Zhihong Liu,
Nobufusa Iwanishi,
Norio Koike,
Hirokazu Yonezawa,
Yoshiyuki Kawakami:
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design.
ISQED 2000: 73-80 |
