| 2008 |
|---|
| 5 | EE | Masanori Kurimoto,
Hiroaki Suzuki,
Rei Akiyama,
Tadao Yamanaka,
Haruyuki Ohkuma,
Hidehiro Takata,
Hirofumi Shinohara:
Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.
DAC 2008: 884-889 |
| 4 | EE | Hiroaki Suzuki,
Masanori Kurimoto,
Tadao Yamanaka,
Hidehiro Takata,
Hiroshi Makino,
Hirofumi Shinohara:
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
ISLPED 2008: 15-20 |
| 2007 |
|---|
| 3 | EE | Kazutami Arimoto,
Toshihiro Hattori,
Hidehiro Takata,
Atsushi Hasegawa,
Toru Shimizu:
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Transactions 90-C(4): 657-665 (2007) |
| 2005 |
|---|
| 2 | EE | Niichi Itoh,
Yasumasa Tsukamoto,
Takeshi Shibagaki,
Koji Nii,
Hidehiro Takata,
Hiroshi Makino:
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
ISCAS (1) 2005: 73-76 |
| 1991 |
|---|
| 1 | | Toshiyuki Tamura,
Shinji Komori,
Fumiyasu Asai,
Hirono Tsubota,
Hisakazu Sato,
Hidehiro Takata,
Yoshihiro Seguchi,
Takeshi Tokuda,
Hiroaki Terada:
A Data-Driven Architecture for Distributed Parallel Processing.
ICCD 1991: 218-224 |
