| 2008 |
|---|
| 76 | | Hasitha Muthumala Waidyasooriya,
Masanori Hariyama,
Michitaka Kameyama:
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning.
ERSA 2008: 201-207 |
| 75 | | Masanori Hariyama,
Shota Ishihara,
Noriaki Idobata,
Michitaka Kameyama:
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
ERSA 2008: 309-310 |
| 74 | EE | Masanori Hariyama,
Kensaku Yamashita,
Michitaka Kameyama:
FPGA implementation of a vehicle detection algorithm using three-dimensional information.
IPDPS 2008: 1-5 |
| 73 | EE | Nobuaki Okada,
Michitaka Kameyama:
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.
ISMVL 2008: 180-185 |
| 72 | EE | Masanori Hariyama,
Naoto Yokoyama,
Michitaka Kameyama:
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling.
IEICE Transactions 91-C(4): 479-486 (2008) |
| 71 | EE | Hasitha Muthumala Waidyasooriya,
Weisheng Chong,
Masanori Hariyama,
Michitaka Kameyama:
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment.
IEICE Transactions 91-C(4): 517-525 (2008) |
| 2007 |
|---|
| 70 | EE | Nobuaki Okada,
Michitaka Kameyama:
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.
ISMVL 2007: 25 |
| 69 | EE | Tasuku Ito,
Michitaka Kameyama:
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation.
ISMVL 2007: 39 |
| 68 | EE | Michitaka Kameyama:
Special Section on VLSI Technology toward Frontiers of New Market.
IEICE Transactions 90-C(10): 1849 (2007) |
| 2006 |
|---|
| 67 | EE | W. H. Muthumala,
Masanori Hariyama,
Michitaka Kameyama:
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design.
APCCAS 2006: 1264-1267 |
| 66 | EE | Masanori Hariyama,
Michitaka Kameyama:
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.
APCCAS 2006: 1803-1806 |
| 65 | EE | Yoshihiro Nakatani,
Masanori Hariyama,
Michitaka Kameyama:
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal.
IPDPS 2006 |
| 64 | EE | Haque Mohammad Munirul,
Michitaka Kameyama:
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.
ISMVL 2006: 13 |
| 63 | EE | Yoshihiro Nakatani,
Masanori Hariyama,
Michitaka Kameyama:
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
ISMVL 2006: 17 |
| 62 | EE | Haque Mohammad Munirul,
Tomoaki Hasegawa,
Michitaka Kameyama:
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.
ISMVL 2006: 6 |
| 61 | EE | Masanori Hariyama,
Michitaka Kameyama,
Yasuhiro Kobayashi:
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors.
ISVLSI 2006: 193-198 |
| 60 | EE | Masanori Hariyama,
Shigeo Yamadera,
Michitaka Kameyama:
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.
IEICE Transactions 89-C(11): 1551-1558 (2006) |
| 59 | EE | Masanori Hariyama,
Sho Ogata,
Michitaka Kameyama:
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates.
IEICE Transactions 89-C(11): 1655-1661 (2006) |
| 2005 |
|---|
| 58 | EE | Weisheng Chong,
Sho Ogata,
Masanori Hariyama,
Michitaka Kameyama:
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory.
IPDPS 2005 |
| 57 | EE | Yuya Homma,
Michitaka Kameyama,
Yoshichika Fujioka,
Nobuhiro Tomabechi:
VLSI architecture based on packet data transfer scheme and its application.
ISCAS (2) 2005: 1786-1789 |
| 56 | EE | Tomoaki Hasegawa,
Yuya Homma,
Michitaka Kameyama:
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.
ISMVL 2005: 114-119 |
| 55 | EE | Haque Mohammad Munirul,
Tomoaki Hasegawa,
Michitaka Kameyama:
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.
ISMVL 2005: 120-125 |
| 54 | EE | Masanori Hariyama,
Weisheng Chong,
Sho Ogata,
Michitaka Kameyama:
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.
ISVLSI 2005: 46-50 |
| 53 | EE | Masanori Hariyama,
Tetsuya Aoyama,
Michitaka Kameyama:
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages.
IEEE Trans. Computers 54(6): 642-650 (2005) |
| 52 | EE | Weisheng Chong,
Masanori Hariyama,
Michitaka Kameyama:
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages.
IEICE Transactions 88-A(12): 3298-3305 (2005) |
| 51 | EE | Masanori Hariyama,
Yasuhiro Kobayashi,
Haruka Sasaki,
Michitaka Kameyama:
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture.
IEICE Transactions 88-A(12): 3516-3522 (2005) |
| 50 | EE | Masanori Hariyama,
Haruka Sasaki,
Michitaka Kameyama:
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access.
IEICE Transactions 88-D(7): 1486-1491 (2005) |
| 2004 |
|---|
| 49 | EE | Haque Mohammad Munirul,
Michitaka Kameyama:
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic.
ISMVL 2004: 26-30 |
| 48 | EE | Haque Mohammad Munirul,
Michitaka Kameyama:
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications.
ISMVL 2004: 328-333 |
| 47 | EE | Weisheng Chong,
Masanori Hariyama,
Michitaka Kameyama:
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.
ISVLSI 2004: 243-248 |
| 46 | EE | Naotaka Ohsawa,
Osamu Sakamoto,
Masanori Hariyama,
Michitaka Kameyama:
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.
ISVLSI 2004: 258-259 |
| 2003 |
|---|
| 45 | EE | Takahiro Hanyu,
Akira Mochizuki,
Michitaka Kameyama:
Multiple-Valued Dynamic Source-Coupled Logic.
ISMVL 2003: 207-212 |
| 44 | EE | Takahiro Hanyu,
Tomohiro Takahashi,
Michitaka Kameyama:
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.
ISMVL 2003: 99-104 |
| 2002 |
|---|
| 43 | EE | Hiromitsu Kimura,
Takahiro Hanyu,
Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.
ISMVL 2002: 161- |
| 42 | EE | Tsukasa Ike,
Takahiro Hanyu,
Michitaka Kameyama:
Fully Source-Coupled Logic Based Multiple-Valued VLSI.
ISMVL 2002: 270-275 |
| 41 | EE | Naotaka Ohsawa,
Masanori Hariyama,
Michitaka Kameyama:
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.
ISVLSI 2002: 95-100 |
| 2001 |
|---|
| 40 | | Masanori Hariyama,
Toshiki Takeuchi,
Michitaka Kameyama:
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection.
ICRA 2001: 1168-1173 |
| 39 | | Takahiro Hanyu,
Michitaka Kameyama,
Katsuhiko Shimabukuro,
C. Zukeran:
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.
ISMVL 2001: 167-172 |
| 38 | | Tsukasa Ike,
Takahiro Hanyu,
Michitaka Kameyama:
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources.
ISMVL 2001: 21-26 |
| 2000 |
|---|
| 37 | EE | Takahiro Hanyu,
Tsukasa Ike,
Michitaka Kameyama:
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.
ISMVL 2000: 382- |
| 36 | EE | Takahiro Hanyu,
Hiromitsu Kimura,
Michitaka Kameyama:
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.
ISMVL 2000: 423-429 |
| 35 | EE | Shunichi Kaeriyama,
Takahiro Hanyu,
Michitaka Kameyama:
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.
ISMVL 2000: 438- |
| 34 | EE | Takahiro Hanyu,
Tsukasa Ike,
Michitaka Kameyama:
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.
PRDC 2000: 27-36 |
| 33 | EE | Masanori Hariyama,
Seunghwan Lee,
Michitaka Kameyama:
Architecture of a high-performance stereo vision VLSI processor.
Advanced Robotics 14(5): 329-332 (2000) |
| 1999 |
|---|
| 32 | EE | Takahiro Hanyu,
Tsukasa Ike,
Michitaka Kameyama:
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.
ISMVL 1999: 275-279 |
| 31 | EE | Takahiro Hanyu,
Hiromitsu Kimura,
Michitaka Kameyama:
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.
ISMVL 1999: 30-35 |
| 30 | EE | Yoshichika Fujioka,
Michitaka Kameyama:
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture.
Systems and Computers in Japan 30(12): 43-51 (1999) |
| 1998 |
|---|
| 29 | | Masanori Hariyama,
Michitaka Kameyama:
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products.
ICRA 1998: 3691-3696 |
| 28 | EE | Takahiro Hanyu,
Takahiro Saito,
Michitaka Kameyama:
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic.
ISMVL 1998: 134-139 |
| 27 | EE | Takahiro Hanyu,
Kaname Teranishi,
Michitaka Kameyama:
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.
ISMVL 1998: 270-275 |
| 26 | EE | Takahiro Saito,
Takahiro Hanyu,
Michitaka Kameyama:
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application.
Systems and Computers in Japan 29(11): 40-47 (1998) |
| 25 | EE | Takahiro Hanyu,
Kaname Teranishi,
Michitaka Kameyama:
Design and evaluation of a digit-parallel multiple-valued content-addressable memory.
Systems and Computers in Japan 29(11): 48-54 (1998) |
| 1997 |
|---|
| 24 | EE | Takahiro Hanyu,
Manabu Arakaki,
Michitaka Kameyama:
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.
ISMVL 1997: 175- |
| 23 | EE | Masanori Hariyama,
Yuichi Araumi,
Michitaka Kameyama:
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects.
Systems and Computers in Japan 28(2): 54-61 (1997) |
| 1996 |
|---|
| 22 | EE | Masami Nakajima,
Michitaka Kameyama:
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy.
ISMVL 1996: 104-109 |
| 21 | EE | Takahiro Hanyu,
Manabu Arakaki,
Michitaka Kameyama:
Quaternary Universal-Literal CAM for Cellular Logic Image Processing.
ISMVL 1996: 224-229 |
| 20 | | Shoji Kawahito,
Makoto Ishida,
Tasuro Nakamura,
Michitaka Kameyama,
Tatsuo Higuchi:
Author's Reply.
IEEE Trans. Computers 45(5): 639 (1996) |
| 1995 |
|---|
| 19 | EE | M. Ryu,
Michitaka Kameyama:
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices.
ISMVL 1995: 20- |
| 18 | EE | Takahiro Hanyu,
Akira Mochizuki,
Michitaka Kameyama:
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
ISMVL 1995: 64- |
| 17 | EE | Xiaowei Deng,
Takahiro Hanyu,
Michitaka Kameyama:
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.
ISMVL 1995: 92-97 |
| 1994 |
|---|
| 16 | | Takahiro Hanyu,
Akira Mochizuki,
Michitaka Kameyama:
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.
ISMVL 1994: 19-26 |
| 15 | | Masami Nakajima,
Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations.
ISMVL 1994: 223-230 |
| 14 | | Shoji Kawahito,
Makoto Ishida,
Tetsuro Nakamura,
Michitaka Kameyama,
Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers 43(1): 34-42 (1994) |
| 1993 |
|---|
| 13 | | Yoshichika Fujioka,
Michitaka Kameyama:
2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control.
ICRA (3) 1993: 149-154 |
| 12 | | Masami Nakajima,
Michitaka Kameyama:
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations.
ISMVL 1993: 283-288 |
| 1992 |
|---|
| 11 | | Katsuhiko Shimabukuro,
Michitaka Kameyama,
Tatsuo Higuchi:
Design of a Multiple-Valued VLSI Processor for Digital Control.
ISMVL 1992: 322-329 |
| 10 | | Makoto Honda,
Michitaka Kameyama,
Tatsuo Higuchi:
Residue Arithmetic Based Multiple-Valued VLSI Image Processor.
ISMVL 1992: 330-336 |
| 9 | | Saneaki Tamaki,
Michitaka Kameyama,
Tatsuo Higuchi:
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits.
ISMVL 1992: 382-388 |
| 8 | | Takafumi Aoki,
Michitaka Kameyama,
Tatsuo Higuchi:
Interconnection-Free Biomolecular Computing.
IEEE Computer 25(11): 41-50 (1992) |
| 1991 |
|---|
| 7 | | Somchai Kittichaikoonkit,
Michitaka Kameyama,
Tatsuo Higuchi:
High-Performance VLSI Processor for Robot Inverse Dynamics Computation.
ICCD 1991: 608-611 |
| 6 | | Takafumi Aoki,
Michitaka Kameyama,
Tatsuo Higuchi:
Design of Interconnection-Free Biomolecular Computing System.
ISMVL 1991: 173-180 |
| 1990 |
|---|
| 5 | | Michitaka Kameyama:
Toward the Age of Beyond-Binary Electronics and Systems.
ISMVL 1990: 162-166 |
| 4 | | Michitaka Kameyama,
Masahiro Nomura,
Tatsuo Higuchi:
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
ISMVL 1990: 355-362 |
| 1988 |
|---|
| 3 | | Michitaka Kameyama,
Shoji Kawahito,
Tatsuo Higuchi:
A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits.
IEEE Computer 21(4): 43-56 (1988) |
| 1977 |
|---|
| 2 | | Tatsuo Higuchi,
Michitaka Kameyama:
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters.
IEEE Trans. Computers 26(12): 1212-1221 (1977) |
| 1 | | Michitaka Kameyama,
Tatsuo Higuchi:
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module.
IEEE Trans. Computers 26(12): 1297-1302 (1977) |
