12. FCCM 2004:
Napa,
CA,
USA
12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, Proceedings.
IEEE Computer Society 2004, ISBN 0-7695-2230-0 BibTeX
Architecture
- Philip James-Roxby, Gordon J. Brebner, Dennis Bemmann:
Time-Critical Software Deceleration in an FCCM.
3-12
Electronic Edition (link) BibTeX
- André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton:
Design Patterns for Reconfigurable Computing.
13-23
Electronic Edition (link) BibTeX
- Miljan Vuletic, Laura Pozzi, Paolo Ienne:
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.
24-33
Electronic Edition (link) BibTeX
Tools I
Arithmetic I
Communications Applications
Networking I
Applications I
Tools II
Applications II
Arithmetic II
Networking II
Posters
- N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured System Methodology for FPGA Based System-on-A-Chip Design.
271-272
Electronic Edition (link) BibTeX
- Emre Özer, Andy Nisbet, David Gregg:
Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs.
273-274
Electronic Edition (link) BibTeX
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
275-276
Electronic Edition (link) BibTeX
- Gregory V. Larchev, Jason D. Lohn:
Hardware-in-the-Loop Evolution of a 3-bit Multiplier.
277-278
Electronic Edition (link) BibTeX
- Ciaran McIvor, Máire McLoone, John V. McCanny:
FPGA Montgomery Multiplier Architectures - A Comparison.
279-282
Electronic Edition (link) BibTeX
- Sebastian Wallner:
Design Methodology of a Configurable System-on-Chip Architecture.
283-284
Electronic Edition (link) BibTeX
- George A. Constantinides, Abunaser Miah, Nalin Sidahao:
Word-Length Optimization of Folded Polynomial Evaluation.
285-286
Electronic Edition (link) BibTeX
- Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
Migrating Functionality from ROMS to Embedded Multipliers.
287-288
Electronic Edition (link) BibTeX
- David Wentzlaff, Anant Agarwal:
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation.
289-290
Electronic Edition (link) BibTeX
- Valeri F. Tomashau, Tom Kean:
Validation of an Advanced Encryption Standard (AES) IP Core.
291-292
Electronic Edition (link) BibTeX
- Sami Khawam, Tughrul Arslan, Fred Westall:
Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays.
293-295
Electronic Edition (link) BibTeX
- Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis:
The MOLEN Processor Prototype.
296-299
Electronic Edition (link) BibTeX
- Tom Van Court, Yongfeng Gu, Martin C. Herbordt:
FPGA Acceleration of Rigid Molecule Interactions.
300-301
Electronic Edition (link) BibTeX
- Phil James-Roxby, Paul R. Schumacher, Charlie Ross:
A Single Program Multiple Data Parallel Processing Platform for FPGAs.
302-303
Electronic Edition (link) BibTeX
- Sebastian Lange, Martin Middendorf:
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration.
304-305
Electronic Edition (link) BibTeX
- Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz:
A Generator of High-Speed Floating-Point Modules.
306-307
Electronic Edition (link) BibTeX
- Alireza Hodjat, Ingrid Verbauwhede:
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA.
308-309
Electronic Edition (link) BibTeX
- Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak:
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding.
310-311
Electronic Edition (link) BibTeX
- Dirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf:
Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems.
312-315
Electronic Edition (link) BibTeX
- Long Bu, John A. Chandy:
FPGA Based Network Intrusion Detection using Content Addressable Memories.
316-317
Electronic Edition (link) BibTeX
- Charlie Ross, A. P. Wim Böhm:
Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems.
318-319
Electronic Edition (link) BibTeX
- Jianchun Li, Christos A. Papachristou, Raj Shekhar:
A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing.
320-321
Electronic Edition (link) BibTeX
- Michael Attig, Sarang Dharmapurikar, John W. Lockwood:
Implementation Results of Bloom Filters for String Matching.
322-323
Electronic Edition (link) BibTeX
- Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson:
An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic.
324-325
Electronic Edition (link) BibTeX
- Rajarshi Mukherjee, Seda Ogrenci Memik:
Power Management for FPGAs: Power-Driven Design Partitioning.
326-327
Electronic Edition (link) BibTeX
- Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
328-329
Electronic Edition (link) BibTeX
- Deepak Boppana, Kully Dhanoa, Jesse Kempa:
FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm.
330-331
Electronic Edition (link) BibTeX
- Andrea Cappelli, Andrea Lodi, Claudio Mucci, Mario Toma, Fabio Campi:
A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow.
332-333
Electronic Edition (link) BibTeX
- Haoyu Song, Jing Lu, John W. Lockwood, James Moscola:
Secure Remote Control of Field-programmable Network Devices.
334-335
Electronic Edition (link) BibTeX
- Neil Steiner, Peter M. Athanas:
An Alternate Wire Database for Xilinx FPGAs.
336-337
Electronic Edition (link) BibTeX
- Sumit Mohanty, Viktor K. Prasanna:
Duty Cycle Aware Application Design using FPGAs.
338-339
Electronic Edition (link) BibTeX
- Shawn Phillips, Akshay Sharma, Scott Hauck:
Automating the Layout of Reconfigurable Subsystems Via Template Reduction.
340-341
Electronic Edition (link) BibTeX
- Matthias Dyer, Marco Platzner, Lothar Thiele:
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine.
342-344
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:11:54 2009
by Michael Ley (ley@uni-trier.de)