Integration, Volume 30

Volume 30, Number 1, November 2000

• Wai-Kei Mak, D. F. Wong:
  A fast hypergraph min-cut algorithm for circuit partitioning. 1-11
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• Alejandro F. González, Pinaki Mazumder:
  Redundant arithmetic, algorithms and implementations. 13-53
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• Hasan Ymeri, Bart Nauwelaers, Karen Maex:
  Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function method. 55-63
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• Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar:
  Test-set partitioning for multi-weighted random LFSRs. 65-75
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• Dominique Lavenier:
  An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions. 77-89
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• G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni:
  Management of charge pump circuits. 91-101
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Volume 30, Number 2, October 2001

• Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson:
  Delay-insensitive gate-level pipelining. 103-131
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• Hasan Ymeri, Bart Nauwelaers, Karen Maex:
  Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate. 133-141
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• Xiaoping Tang, D. F. Wong:
  Network flow based buffer planning. 143-155
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• Soumen Maity, Bimal K. Roy, Amiya Nayak:
  Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links. 157-168
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• Kiamal Z. Pekmestzi, Nikos K. Moshopoulos:
  A bit-interleaved systolic architecture for a high-speed RSA system. 169-175
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