ICPP 1990:
Urbana-Champaign,
IL,
USA
Benjamin W. Wah (Ed.):
Proceedings of the 1990 International Conference on Parallel Processing, Volume 1: Architectur, Urbana-Champaign, IL, August 1990.
Pennsylvania State University Press 1990, ISBN 0-271-00728-1 BibTeX
@proceedings{DBLP:conf/icpp/1990-1,
editor = {Benjamin W. Wah},
title = {Proceedings of the 1990 International Conference on Parallel
Processing, Volume 1: Architectur, Urbana-Champaign, IL, August
1990},
booktitle = {ICPP (1)},
publisher = {Pennsylvania State University Press},
year = {1990},
isbn = {0-271-00728-1},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Task Scheduling
Synchronization in Mulitprocessors
Task Scheduling II
Efficient Memory Access Methods
Mapping Algorithms to Parallel Systems I
Application-Driven Architectures
Performance Modeling and Evaluation I
Performance Modeling and Evaluation II
Load Balancing on Hypercubes
Mapping Algorithms to Parallel Systems II
Fault Detection,
Diagnosis,
and Recovery Schemes
Routing in Hypercubes
Cache Coherence
Routing and Permutation in Interconnection Networks
Generalized Interconnection Networks I
Generalized Interconnection Networks II
Data-Driven and Communication Architectures
Fault Tolerant Interconnection Networks
Special-Purpose VLSI Array Processors
Parallel Symbolic Processing Architectures
Multicomputer Network Design
Massively Parallel Systems
- Maya Gokhale, William Holmes, Andrew Kopser, Dick Kunze, Daniel P. Lopresti, Sara Lucas, Ronald Minnich, Peter Olsen:
SPLASH: A Reconfigurable Linear Logic Array.
526-532 BibTeX
- Robert W. Horst:
Task Flow Computer Architecture.
533-540 BibTeX
- Isaac D. Scherson, David A. Kramer, Brian D. Alleyne:
A Fine-Grain Bit-Parallel, Word-Parallel, Massively-Parallel Associative Processor.
541-544 BibTeX
- Behrooz Parhami:
Systolic Associative Memories.
545-548 BibTeX
Multiprocessing and Parallel Processing
- David R. Barach, Robert Wells, Thomas Uban, James Gibson:
Highly Parallel Virtual Memory Management on the TC2000.
549-550 BibTeX
- Min-You Wu, Wei Shu:
A Dynamic Partitioning Strategy on Distributed Memory Systems.
551-552 BibTeX
- Eugene D. Brooks III, Joseph E. Hoag:
A Scalable Coherent Cache System With Incomplete Directory State.
553-554 BibTeX
- Michael W. Strevell, Harvey G. Cragon:
Data Type Coherency in Heterogeneous Shared Memory Multiprocessors.
555-556 BibTeX
- Brian Waldecker, Mario J. Gonzalez Jr.:
Reliability in Bus Structured and Completely Connected Distributed Systems.
557-558 BibTeX
- Salim Hariri, A. Gaber Mohamed, Hasan B. Mutlu:
Modeling Availability of Parallel Computers.
559-560 BibTeX
- Jeff D. Martens, D. N. Jayasimha:
A Tree Structured Hierarchical Memory Multiprocessor.
561-562 BibTeX
- David J. Lilja, Pen-Chung Yew:
Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors.
563-564 BibTeX
- Tein-Hsiang Lin, Adly T. Fam:
A Hierarchical Approach for the Design of Two-Dimensional Fault-Tolerant Systolic Arrays.
565-566 BibTeX
- Hiroshi Nishikawa, Kazuo Sakushima, Takashi Hamada, Motohiro Misawa, Katsura Kawakami:
Grain Size Oriented Pipeline Machine - GRAPE.
567-568 BibTeX
Task Scheduling
Interconnection Networks
Application-Specific Parallel Architectures and Systems
- Peter Wohl, Thomas W. Christopher:
SIMD Neural Net Mapping on MIMD Architectures.
587-588 BibTeX
- Zhiyong Liu, Jia-Huai You:
Finding the Shortest Path in ESMSS Network.
589-590 BibTeX
- Hamid R. Arabnia:
A Multi-Ring Transputer Network for the Arbitrary Rotation of Raster Images.
591-592 BibTeX
- Won S. Lee, Rangasami L. Kashyap, Phillip C.-Y. Sheu:
On Optimal Evaluation of Conjunctive Queries in Parallel Environments.
593-594 BibTeX
- Reza Hashemian:
Parallel Addition Using Pipeline Structure.
595-596 BibTeX
- Zhenqiang Fan, Kam-Hoi Cheng:
A Generalized Simultaneous Access Dictionary Machine.
597-598 BibTeX
- Jun Gu, Rok Sosic:
A Parallel Optimal Arc Consistency Algorithm.
599-600 BibTeX
- Mahdi Abdelguerfi, H. Munaf:
A Bit-Sliced Special Purpose Unit for Relational Database Aggregation Operations.
601-602 BibTeX
- Yaohon Chu, Kozo Itano:
Coprocessor Parallel Architecture for Compilation.
603-604 BibTeX
- Nimish R. Shah, Lalit M. Patnaik:
SPARCS: A System for Parallel Architecture Simulation.
605-606 BibTeX
- Aloke Guha:
A Fine-Grained Parallel Architecture for Graph Reduction.
607-608 BibTeX
- Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber:
The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration.
609-610 BibTeX
- Michael Butler, Yale N. Patt:
An Area-Efficient Register Alias Table for Implementing HPS.
611-612 BibTeX
- Katsuto Nakajima, Nobuyuki Ichiyoshi:
Evaluation of Inter-processor Communication in the KL1 Implementation on the Multi-PSI.
613-614 BibTeX
- Michael A. Young:
Livermore Loops on the Connection Machine.
615-616 BibTeX
- Jean Frédéric Myoupo:
A Linear Systolic Array for Transitive Closure Problems.
617-618 BibTeX
- Irving S. Reed, Xuemin Chen, Trieu-Kien Truong:
An Integral Microcontroller Architecture Designed by Using the Register Transfer Language for VLSI Chips.
619-620 BibTeX
Copyright © Sat May 16 23:21:00 2009
by Michael Ley (ley@uni-trier.de)
