SoCC 2008:
Newport Beach,
CA,
USA
21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings.
IEEE 2008 BibTeX
Keynotes / Plenary Presentations
Embedded Systems and Multicore Architectures
System Level Design
- Yibo Chen, Jin Ouyang, Yuan Xie:
ILP-based scheme for timing variation-aware scheduling and resource binding.
27-30
Electronic Edition (link) BibTeX
- Ying Yi, Wei Han, Adam Major, Ahmet T. Erdogan, Tughrul Arslan:
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer.
31-34
Electronic Edition (link) BibTeX
- Mark Muir, Iain Lindsay, Tughrul Arslan, Ioannis Nousias, Sami Khawam, Mark Milward, Nazish Aslam, Adam Major:
Extensible software emulator for reconfigurable instruction cell based processors.
35-40
Electronic Edition (link) BibTeX
- Wei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Edorgan:
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors.
41-44
Electronic Edition (link) BibTeX
Signal Integrity
Network on Chip
Posters
- Hermann Kopetz, Christian El Salloum, Bernhard Huber, Roman Obermaisser, Christian Paukovits:
Composability in the time-triggered system-on-chip architecture.
87-90
Electronic Edition (link) BibTeX
- Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan:
A systematic approach to synthesis of verification test-suites for modular SoC designs.
91-96
Electronic Edition (link) BibTeX
- Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang:
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration.
97-100
Electronic Edition (link) BibTeX
- Ji-Man Park, Sung-Ik Jun:
A resistance deviation-to-time interval converter for resistive sensors.
101-104
Electronic Edition (link) BibTeX
- Seth H. Groder, Kenneth W. Hsu:
Design methodolgy for HD Photo compression algorithm targeting a FPGA.
105-108
Electronic Edition (link) BibTeX
- Shao-Min Hsu, Yuyu Chang, John Choma Jr.:
Design of low flicker noise active CMOS mixer.
109-112
Electronic Edition (link) BibTeX
- Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao:
65NM sub-threshold 11T-SRAM for ultra low voltage applications.
113-118
Electronic Edition (link) BibTeX
- Phillip David Ferguson, Tughrul Arslan, Ahmet T. Erdogan, Andrew Parmley:
Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA.
119-122
Electronic Edition (link) BibTeX
- Tuan Vu Cao, Dag T. Wisland, Tor Sverre Lande, Farshad Moradi, Young Hee Kim:
Novel start-up circuit with enhanced power-up characteristic for bandgap references.
123-126
Electronic Edition (link) BibTeX
- Iris Hui-Ru Jiang, Shung-Wei Lin, Yen-Ting Yu:
Unification of obstacle-avoiding rectilinear Steiner tree construction.
127-130
Electronic Edition (link) BibTeX
- Daisaku Seto, Minoru Watanabe:
Analysis of retention time under multi-configuration on a DORGA.
131-134
Electronic Edition (link) BibTeX
- Hanni Bagnordi, Mabo Ito:
Performance evaluation of a FFT using adpative clocking.
135-138
Electronic Edition (link) BibTeX
- Farhad Alibeygi Parsan, Ahmad Ayatollahi:
A comparator-based switched-capacitor integrator using a new charge control circuit.
139-142
Electronic Edition (link) BibTeX
- Ethiopia Nigussie, Juha Plosila, Jouni Isoaho:
Area efficient delay-insensitive and differential current sensing on-chip interconnect.
143-146
Electronic Edition (link) BibTeX
- Basab Datta, Wayne P. Burleson:
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO.
147-150
Electronic Edition (link) BibTeX
- Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede:
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices.
151-154
Electronic Edition (link) BibTeX
- Ramin Shariat-Yazdi, Tad Kwasniewski:
A multi-mode sphere detector architecture for WLAN applications.
155-158
Electronic Edition (link) BibTeX
- Srivathsan Krishnamohan, Nihar R. Mahapatra:
Slack redistribution in pipelined circuits for enhanced soft-error rate reduction.
159-162
Electronic Edition (link) BibTeX
- Khalid Latif, Moazzam Niazi, Hannu Tenhunen, Tiberiu Seceleanu, Sakir Sezer:
Application development flow for on-chip distributed architectures.
163-168
Electronic Edition (link) BibTeX
- Md. Mahbub Reja, Kambiz K. Moez, Igor M. Filanovsky:
A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applications.
169-172
Electronic Edition (link) BibTeX
Low Power Circuit Design
H.264
Low Power Design Methodologies
Video Processing
SRAM Memory Technologies
- Hao-I Yang, Ssu-Yun Lai, Wei Hwang:
Low-power floating bitline 8-T SRAM design with write assistant circuits.
239-242
Electronic Edition (link) BibTeX
- Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
243-246
Electronic Edition (link) BibTeX
- Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi:
Low power 8T SRAM using 32nm independent gate FinFET technology.
247-250
Electronic Edition (link) BibTeX
- Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Failure analysis for ultra low power nano-CMOS SRAM under process variations.
251-254
Electronic Edition (link) BibTeX
Analog and Mixed-Signal 1
Reconfigurable Computing 1
Analog and Mixed Signal 2
Reconfigurable Computing 2
Analog and Mixed Signal 3
- Hong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng, Chih-Yuan Hsu:
A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator.
333-336
Electronic Edition (link) BibTeX
- Chorng-Sii Hwang, Huan-Chun Li, Hen-Wai Tsao:
A spread spectrum clock generator using digital modulation scheme.
337-340
Electronic Edition (link) BibTeX
- Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin:
All digital time-to-digital converter using single delay-locked loop.
341-344
Electronic Edition (link) BibTeX
- Seiede Fateme Ashrafi, Seied Mojtaba Atarodi, Mohammad Chahardori:
New low voltage, high PSRR, CMOS bandgap voltage reference.
345-348
Electronic Edition (link) BibTeX
CAD
- Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman Solovyev, Jacob A. Abraham:
A timing methodology considering within-die clock skew variations.
351-356
Electronic Edition (link) BibTeX
- Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao:
X-clock routing based on pattern matching.
357-360
Electronic Edition (link) BibTeX
- Di Phan, Christopher J. Berry, Frank Malgioglio, Alan P. Wagstaff:
An automated design method for chip power distribution.
361-364
Electronic Edition (link) BibTeX
Communication and Processing
Tutorials
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by Michael Ley (ley@uni-trier.de)
