11. IOLTS 2005:
Saint Raphael,
France
11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France.
IEEE Computer Society 2005, ISBN 0-7695-2406-0 BibTeX
Introduction
Session 1:
Transient Fault Modeling and Analysis
Session 2:
Transient Faults' Hardening Techniques
Session 3:
SEU Effects in FPGAs
- Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes:
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.
43-48
Electronic Edition (link) BibTeX
- Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi:
Heavy Ion Effects on Configuration Logic of Virtex FPGAs.
49-53
Electronic Edition (link) BibTeX
- Matteo Sonza Reorda, Luca Sterpone, Massimo Violante:
Efficient Estimation of SEU Effects in SRAM-Based FPGAs.
54-59
Electronic Edition (link) BibTeX
Special Session 1:
Robust Design Techniques for Soft Errors
Special Session 2:
Simulation and Mitigation of Single Event Effects
- Lorena Anghel, Michael Nicolaidis:
Simulation and Mitigation of Single Event Effects.
81
Electronic Edition (link) BibTeX
- Frederic Wrobel:
Use of Nuclear Codes for Neutron-Induced Nuclear Reactions in Microelectronics.
82-86
Electronic Edition (link) BibTeX
- G. Hubert, N. Buard, C. Weulersse, T. Carriere, M.-C. Palau, J.-M. Palau, D. Lambert, J. Baggio, F. Wrobel, F. Saigne, R. Gaillard:
A Review of DASIE Code Family: Contribution to SEU/MBU Understanding.
87-94
Electronic Edition (link) BibTeX
- Michael Nicolaidis:
Design for Mitigation of Single Event Effects.
95-96
Electronic Edition (link) BibTeX
Special Session 3:
Self Calibrating Design
Special Session 4:
Secure Implementations
Session 4:
On-Line Testing for Secure and Asynchronous Chips
Session 5:
Self Checking Strategies
- Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou:
Fast, Parallel Two-Rail Code Checker with Enhanced Testability.
149-156
Electronic Edition (link) BibTeX
- Julian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev:
Power-Balanced Self Checking Circuits for Cryptographic Chips.
157-162
Electronic Edition (link) BibTeX
- Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni:
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization.
163-168
Electronic Edition (link) BibTeX
Session 6:
Process Variations,
Leakage,
and Power Supply Noise Detection and Tolerance
Session 7:
Posters
- Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache:
Modeling of Transients Caused by a Laser Attack on Smart Cards.
193-194
Electronic Edition (link) BibTeX
- Riccardo Mariani, Gabriele Boschi:
Scrubbing and Partitioning for Protection of Memory Systems.
195-196
Electronic Edition (link) BibTeX
- Andrzej Krasniewski:
A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory.
197-198
Electronic Edition (link) BibTeX
- Amandeep Singh, Debashish Bose:
A Software Based Online Memory Test for Highly Available Systems.
199-200
Electronic Edition (link) BibTeX
- Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano:
Design of a Self Checking Reed Solomon Encoder.
201-202
Electronic Edition (link) BibTeX
- Kentaroh Katoh, Abderrahim Doumar, Hideo Ito:
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.
203-204
Electronic Edition (link) BibTeX
- Amir Rajabzadeh:
A 32-Bit COTS-Based Fault-Tolerant Embedded System.
205-206
Electronic Edition (link) BibTeX
- Fabian Vargas, D. L. Cavalcante, E. Gatti, Dárcio Prestes, D. Lupi:
On the Proposition of an EMI-Based Fault Injection Approach.
207-208
Electronic Edition (link) BibTeX
Panel
Session 8:
Testing Issues
Session 9:
SoC Testing and Fault Tolerance
Session 10:
Multiple Bit Upset Evaluation and Correction
Session 11:
Timing,
Yield,
and Reliability Issues
- Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
275-280
Electronic Edition (link) BibTeX
- M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test.
281-286
Electronic Edition (link) BibTeX
- Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy:
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.
287-292
Electronic Edition (link) BibTeX
Special Session 5:
Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing
Copyright © Sat May 16 23:24:15 2009
by Michael Ley (ley@uni-trier.de)
