| 2007 |
|---|
| 9 | EE | Robert Ronan,
Colm O'Eigeartaigh,
Colin C. Murphy,
Tim Kerins,
Paulo S. L. M. Barreto:
A Reconfigurable Processor for the Cryptographic nT Pairing in Characteristic 3.
ITNG 2007: 11-16 |
| 8 | EE | Robert P. McEvoy,
Michael Tunstall,
Colin C. Murphy,
William P. Marnane:
Differential Power Analysis of HMAC Based on SHA-2, and Countermeasures.
WISA 2007: 317-332 |
| 7 | EE | Maurice Keller,
Robert Ronan,
William P. Marnane,
Colin C. Murphy:
Hardware architectures for the Tate pairing over GF(2m).
Computers & Electrical Engineering 33(5-6): 392-406 (2007) |
| 6 | EE | Catriona M. Lucey,
Colin C. Murphy:
Constraint Based Design of Two-Channel Paraunitary Filter Banks of a Given Length Over GF(2r).
IEEE Transactions on Signal Processing 55(5-1): 1940-1944 (2007) |
| 5 | EE | Robert Ronan,
Colm O'Eigeartaigh,
Colin C. Murphy,
Michael Scott,
Tim Kerins:
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve.
Journal of Systems Architecture 53(2-3): 85-98 (2007) |
| 2006 |
|---|
| 4 | EE | Robert P. McEvoy,
Francis M. Crowe,
Colin C. Murphy,
William P. Marnane:
Optimisation of the SHA-2 Family of Hash Functions on FPGAs.
ISVLSI 2006: 317-322 |
| 3 | EE | Robert Ronan,
Colm O'Eigeartaigh,
Colin C. Murphy,
Michael Scott,
Tim Kerins,
William P. Marnane:
An Embedded Processor for a Pairing-Based Cryptosystem.
ITNG 2006: 192-197 |
| 2 | | Robert P. McEvoy,
Colin C. Murphy:
Efficient All-or-Nothing Encryption Using CTR Mode.
SECRYPT 2006: 237-245 |
| 1999 |
|---|
| 1 | | Emanuel M. Popovici,
Patrick Fitzpatrick,
Colin C. Murphy:
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding.
FPL 1999: 353-358 |
