| 2008 |
|---|
| 10 | EE | Gang-Neng Sung,
Yan-Jhin Ciou,
Chua-Chin Wang:
A power-aware 2-dimensional bypassing multiplier using cell-based design flow.
ISCAS 2008: 3338-3341 |
| 9 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Chi-Chun Huang,
Ching-Li Lee,
Tian-Hau Chen,
Wun-Ji Lin,
Ron Hu:
A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors.
Journal of Circuits, Systems, and Computers 17(5): 943-956 (2008) |
| 8 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Pai-Li Liu:
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.
Signal Processing Systems 52(2): 127-135 (2008) |
| 2007 |
|---|
| 7 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Kuan-Wen Fang,
Sheng-Lun Tseng:
A Low-power Sensorless Inverter Controller of Brushless DC Motors.
ISCAS 2007: 2435-2438 |
| 6 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Jian-Ming Huang,
Li-Pin Lin:
An 80MHz PLL with 72.7ps peak-to-peak jitter.
Microelectronics Journal 38(6-7): 716-721 (2007) |
| 2006 |
|---|
| 5 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Ming-Kai Chang,
Ching-Li Lee,
Cheng-Mu Wu,
Ju-Ya Chen:
A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers.
APCCAS 2006: 1112-1115 |
| 4 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Ming-Kai Chang,
Ying-Yu Shen:
Engery-Efficient Double-Edge Triggered Flip-Flop Design.
APCCAS 2006: 1791-1794 |
| 3 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Tzung-Je Lee,
Cheng-Mu Wu,
Gang-Neng Sung,
Kuan-Wen Fang,
Sheng-Lun Tseng,
Jia-Jin Chen:
An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording.
APCCAS 2006: 682-685 |
| 2 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Jia-Hao Li:
Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263.
IIH-MSP 2006: 483-486 |
| 1 | EE | Chua-Chin Wang,
Gang-Neng Sung:
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology.
ISVLSI 2006: 405-410 |
