2007 |
11 | EE | Camille Leroux,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
Towards Gb/s turbo decoding of product code onto an FPGA device.
ISCAS 2007: 909-912 |
2006 |
10 | EE | Irene M. Mahafeno,
Charlotte Langlais,
Christophe Jégo:
Reduced Complexity Iterative Multi-User Detector for IDMA (Interleave-Division Multiple Access) System.
GLOBECOM 2006 |
9 | EE | Catherine Dezan,
Christophe Jégo,
Bernard Pottier,
Christophe Gouyen,
Loïc Lagadec:
The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA.
HICSS 2006 |
8 | EE | Erwan Piriou,
Christophe Jégo,
Patrick Adde,
Raphaël Le Bidan,
Michel Jézéquel:
Efficient architecture for Reed Solomon block turbo code.
ISCAS 2006 |
7 | EE | Erwan Piriou,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.
ISVLSI 2006: 430-431 |
6 | | Erwan Piriou,
Christophe Jégo,
Patrick Adde,
Michel Jézéquel:
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding.
ReCoSoC 2006: 152-159 |
2005 |
5 | EE | Nabil Abdelli,
Pierre Bomel,
Emmanuel Casseau,
Anne-Marie Fouilliart,
Christophe Jégo,
Philippe Kajfasz,
Bertrand Le Gal,
Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards.
DSD 2005: 88-95 |
4 | | Caaliph Andriamisaina,
Catherine Dezan,
Christophe Jégo,
Bernard Pottier:
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit.
ERSA 2005: 263-266 |
2004 |
3 | | Emmanuel Casseau,
Bertrand Le Gal,
Christophe Jégo,
Nathalie Le Heno,
Eric Martin:
Reed-Solomon behavioral virtual component for communication systems.
ISCAS (4) 2004: 173-176 |
2 | | Emmanuel Casseau,
Christophe Jégo,
Eric Martin:
Synthèse architecturale d'applications temps réel pour technologies submicroniques.
Technique et Science Informatiques 23(1): 35-66 (2004) |
1999 |
1 | | Christophe Jégo,
Emmanuel Casseau,
Eric Martin:
Architectural Synthesis with Interconnection Cost Control.
VLSI 1999: 509-520 |