| 2006 |
|---|
| 5 | EE | Nagarajan Ranganathan,
Ravi Namballa,
Narender Hanchate:
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.
ISVLSI 2006: 329-334 |
| 2005 |
|---|
| 4 | EE | Saraju P. Mohanty,
Nagarajan Ranganathan,
Ravi Namballa:
A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design.
IEEE Trans. VLSI Syst. 13(7): 808-818 (2005) |
| 3 | EE | Saraju P. Mohanty,
Nagarajan Ranganathan,
Ravi Namballa:
A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*.
IEEE Trans. VLSI Syst. 13(8): 1002-1012 (2005) |
| 2004 |
|---|
| 2 | EE | Ravi Namballa,
Nagarajan Ranganathan,
Abdel Ejnioui:
Control and Data Flow Graph Extraction for High-Level Synthesis.
ISVLSI 2004: 192 |
| 1 | EE | Saraju P. Mohanty,
Nagarajan Ranganathan,
Ravi Namballa:
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design.
VLSI Design 2004: 1063- |
