Mahnaz Sadoughi Yarandi
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2006
1
EE
Mahnaz Sadoughi Yarandi,
Armin Alaghi
,
Zainalabedin Navabi
: An Optimized BIST Architecture for FPGA Look-Up Table Testing.
ISVLSI 2006
: 420-421
Coauthor
Index
1
Armin Alaghi
[
1
]
2
Zainalabedin Navabi
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
