| |
| 2006 | ||
|---|---|---|
| 2 | EE | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer: LUT-based MPGAs for fast turnaround time conversion flow. ISCAS 2006 |
| 1 | EE | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer: Regular Routing Architecture for a LUT-based MPGA. ISVLSI 2006: 257-262 |
| 1 | Hans-Jörg Pfleiderer | [1] [2] |
| 2 | Michael Scheppler | [1] [2] |
| 3 | Francisco-Javier Veredas | [1] [2] |