| 2006 |
|---|
| 4 | EE | Takashi Nojima,
Nobuto Ono,
Shigetoshi Nakatake,
Toru Fujimura,
Koji Okazaki,
Yoji Kajitani:
Adaptive Porting of Analog IPs with Reusable Conservative Properties.
ISVLSI 2006: 18-23 |
| 3 | EE | Tan Yan,
Shigetoshi Nakatake,
Takashi Nojima:
Formulating the Empirical Strategies in Module Generation of Analog MOS Layout.
ISVLSI 2006: 44-49 |
| 2004 |
|---|
| 2 | EE | Takashi Nojima,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani:
A device-level placement with multi-directional convex clustering.
ACM Great Lakes Symposium on VLSI 2004: 196-201 |
| 1 | EE | Takashi Nojima,
Xiaoke Zhu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani:
Multi-level placement with circuit schema based clustering in analog IC layouts.
ASP-DAC 2004: 406-411 |
