P. V. Srinivas

2006
4	EE	P. V. Srinivas: Chip assembly: a new paradigm in hierarchical physical design. ISPD 2006: 165
2004
3	EE	Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas: Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1256-1263 (2004)
2003
2	EE	Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas: Noise-Aware Driver Modeling for Nanometer Technology. ISQED 2003: 177-182
1993
1		Aditya Agrawal, P. V. Srinivas, G. Sreenivas, Uttiya Dasgupta: LATCHECK: A Latchup Checker for VLSI Layouts. VLSI Design 1993: 230-235

Coauthor Index

1	Aditya Agrawal	[1]
2	Xiaoliang Bai	[2] [3]
3	Rajit Chandra	[2] [3]
4	Uttiya Dasgupta	[1]
5	Sujit Dey	[2] [3]
6	G. Sreenivas	[1]

Colors in the list of coauthors