2008 | ||
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22 | EE | Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid: A table-based method for single-pass cache optimization. ACM Great Lakes Symposium on VLSI 2008: 71-76 |
2007 | ||
21 | EE | Bruno Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araujo, Edna Barros, Willians Azevedo: A computational reflection mechanism to support platform debugging in SystemC. CODES+ISSS 2007: 81-86 |
20 | EE | Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros: A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760 |
19 | EE | Andre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana: Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. IEEE International Workshop on Rapid System Prototyping 2007: 3-9 |
18 | EE | Jordana L. Seixas, Edson Barbosa, Stelita M. da Silva, Paulo Sérgio B. do Nascimento, Vinícius Kursancew, Remy Eskinazi Sant'Anna, Edna Barros, Manoel Eusebio de Lima: Aquarius: a dynamically reconfigurable computing platform. SBCCI 2007: 171-176 |
2006 | ||
17 | EE | Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid: Configurable cache subsetting for fast cache tuning. DAC 2006: 695-700 |
16 | EE | Abel Guilhermino S. Filho, Pablo Viana, Edna Barros, Manoel Eusebio de Lima: Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. SBAC-PAD 2006: 125-132 |
2005 | ||
15 | EE | Danielly Cruz, Edna Barros: Vital Signs Remote Management System for PDAs. DSD 2005: 170-175 |
14 | EE | Cristiano C. de Araujo, Edna Barros, Rodolfo Azevedo, Guido Araujo: Processor Centric Specification and Modelling of MPSoCs. FDL 2005: 303-315 |
13 | EE | Marilia Lima, F. Santos, J. Bione, T. Lins, Edna Barros: IpPROCESS: a Development Process for Soft IP-Cord. FDL 2005: 487-499 |
12 | EE | Marilia Lima, Andre Aziz, Diogo Alves, Patricia Lira, Vitor Schwambach, Edna Barros: ipPROCESS: Using a Process to Teach IP-Core Development. MSE 2005: 27-28 |
11 | EE | Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Guido Araujo, Cristiano C. de Araujo, Edna Barros: The ArchC Architecture Description Language and Tools. International Journal of Parallel Programming 33(5): 453-484 (2005) |
2004 | ||
10 | EE | Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. DATE 2004: 734-735 |
9 | EE | Albano Portela Machado, Paulo Romero Martins Maciel, Edna Barros: A Petri net based method for functional and interconnect units estimation. SMC (5) 2004: 4983-4988 |
8 | EE | Leila Silva, Augusto Sampaio, Edna Barros: A Constructive Approach to Hardware/Software Partitioning. Formal Methods in System Design 24(1): 45-90 (2004) |
2003 | ||
7 | EE | Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Exploring Memory Hierarchy with ArchC. SBAC-PAD 2003: 2-9 |
2001 | ||
6 | Cristiano C. de Araujo, Edna Barros: Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design. VLSI-SOC 2001: 145-156 | |
1998 | ||
5 | EE | Leila Silva, Augusto Sampaio, Edna Barros, Juliano Iyoda: An Algebraic Approach to Combining Processes in a Hardware/Software Partitioning Environment. AMAST 1998: 308-324 |
1997 | ||
4 | EE | Cristiano C. de Araujo, Marcus V. D. dos Santos, Edna Barros: A FPGA-based Implementation of an Intravenous Infusion Controller System. ASAP 1997: 402-411 |
3 | Leila Silva, Augusto Sampaio, Edna Barros: A Normal Form Reduction Strategy for Hardware/Software Partitioning. FME 1997: 624-643 | |
1994 | ||
2 | EE | Edna Barros, Augusto Sampaio: Towards provably correct hardware/software partitioning using occam. CODES 1994: 210-217 |
1 | EE | Xun Xiong, Edna Barros, Wolfgang Rosenstiel: A method for partitioning UNITY language in hardware and software. EURO-DAC 1994: 220-225 |