Volume 25,
Number 1,
January-February 2005
Editor-in-Chief's Message
Micro Law
Features
- James P. G. Sterbenz, Dimitrios Stiliadis:
Guest Editors' Introduction: Hot Interconnects 12.
8-9
Electronic Edition (link) BibTeX
- Venkata Krishnan, David Mayhew:
Localized Congestion Control in Advanced Switching Interconnects.
10-18
Electronic Edition (link) BibTeX
- Jiuxing Liu, Amith R. Mamidala, Abhinav Vishnu, Dhabaleswar K. Panda:
Evaluating InfiniBand Performance with PCI Express.
20-29
Electronic Edition (link) BibTeX
- Thomas H. Dunigan Jr., Jeffrey S. Vetter, James B. White III, Patrick H. Worley:
Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture.
30-40
Electronic Edition (link) BibTeX
- Avinash Karanth Kodi, Ahmed Louri:
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors.
41-49
Electronic Edition (link) BibTeX
- Fang Yu, Randy H. Katz, T. V. Lakshman:
Efficient Multimatch Packet Classification and Lookup with TCAM.
50-59
Electronic Edition (link) BibTeX
- Bharath Madhusudan, John W. Lockwood:
A Hardware-Accelerated System for Real-Time Worm Detection.
60-69
Electronic Edition (link) BibTeX
- Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy, Nick McKeown:
Using Hardware to Configure a Load-Balanced Switch.
70-78
Electronic Edition (link) BibTeX
- Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero:
Better Branch Prediction Through Prophet/Critic Hybrids.
80-89
Electronic Edition (link) BibTeX
- Kyle J. Nesbit, James E. Smith:
Data Cache Prefetching Using a Global History Buffer.
90-97
Electronic Edition (link) BibTeX
Micro Review
Micro Economics
Volume 25,
Number 2,
March-April 2005
Editor-in-Chief's Message
Micro Review
Features
- William J. Dally, Keith Diefendorff:
Hot Chips 16: Power, Parallelism, and Memory Performance.
8-9
Electronic Edition (link) BibTeX
- Cameron McNairy, Rohit Bhatia:
Montecito: A Dual-Core, Dual-Thread Itanium Processor.
10-20
Electronic Edition (link) BibTeX
- Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun:
Niagara: A 32-Way Multithreaded Sparc Processor.
21-29
Electronic Edition (link) BibTeX
- Rajesh Kota, Rich Oehler:
Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems.
30-40
Electronic Edition (link) BibTeX
- John Montrym, Henry P. Moreton:
The GeForce 6800.
41-51
Electronic Edition (link) BibTeX
- Hans Eberle, Sheueling Chang Shantz, Vipul Gupta, Nils Gura, Leonard Rarick, Lawrence Spracklen:
Accelerating Next-Generation Public-Key Cryptosystems on General-Purpose CPUs.
52-59
Electronic Edition (link) BibTeX
- Jorg Keller, Andreas Gravinghoff:
Thread-Based Virtual Duplex Systems in Embedded Environments.
60-69
Electronic Edition (link) BibTeX
Micro Economics
Volume 25,
Number 3,
May-June 2005
Editor-in-Chief's Message
Micro Law
Micro Economics
Micro Review
Features
- Michael J. Flynn, Patrick Hung:
Microprocessor Design Issues: Thoughts on the Road Ahead.
16-31
Electronic Edition (link) BibTeX
- Shailender Chaudhry, Paul Caprioli, Sherman Yip, Marc Tremblay:
High-Performance Throughput Computing.
32-45
Electronic Edition (link) BibTeX
- Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero:
Kilo-Instruction Processors: Overcoming the Memory Wall.
48-57
Electronic Edition (link) BibTeX
- Tilak Agerwala, Siddhartha Chatterjee:
Computer Architecture: Challenges and Opportunities for the Next Decade.
58-69
Electronic Edition (link) BibTeX
- Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
Lifetime Reliability: Toward an Architectural Solution.
70-80
Electronic Edition (link) BibTeX
- Mancia Anguita, J. Manuel Martinez-Lechado:
MP3 Optimization Exploiting Processor Architecture and using Better Algorithms.
81-92
Electronic Edition (link) BibTeX
Micro Innovations
Volume 25,
Number 4,
July-August 2005
Editor-in-Chief's Message
Micro Innovations
Features
- Zhichun Zhu, Xiaodong Zhang:
Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption.
10-19
Electronic Edition (link) BibTeX
- Yen-Jen Chang, Feipei Lai:
Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories.
20-32
Electronic Edition (link) BibTeX
- Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha:
QsNetII: Defining High-Performance Network Design.
34-47
Electronic Edition (link) BibTeX
- Mohammad J. Akhbarizadeh, Mehrdad Nourani, Cyrus D. Cantrell:
Prefix Segregation Scheme for a TCAM-Based IP Forwarding Engine.
48-63
Electronic Edition (link) BibTeX
- Weidong Wu, Jian Shi, Ling Zuo, Bingxin Shi:
Power-Efficient TCAMS for Bursty Access Patterns.
64-72
Electronic Edition (link) BibTeX
Micro Law
Micro Economics
Micro Review
Volume 25,
Number 5,
September-October 2005
Editor-in-Chief's Message
Features
- Kunio Uchiyama, Pradip Bose:
Guest Editors' Introduction: Energy-Efficient Design.
6-9
Electronic Edition (link) BibTeX
- Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman:
Power-Conscious Design of the Cell Processor's Synergistic Processor Element.
10-18
Electronic Edition (link) BibTeX
- Seiji Maeda, Shigehiro Asano, Tomofumi Shimada, Koichi Awazu, Haruyuki Tago:
A Real-Time Software Platform for the Cell Processor.
20-29
Electronic Edition (link) BibTeX
- Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara:
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.
30-38
Electronic Edition (link) BibTeX
- Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi:
Long-Term Workload Phases: Duration Predictions and Applications to DVFS.
39-51
Electronic Edition (link) BibTeX
- Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark:
Formal Control Techniques for Power-Performance Management.
52-62
Electronic Edition (link) BibTeX
- Diana Marculescu, Emil Talpes:
Energy Awareness and Uncertainty in Microarchitecture-Level Design.
64-76
Electronic Edition (link) BibTeX
Micro Law
Micro Innovations
Micro Economics
Volume 25,
Number 6,
November-December 2005
Editor-in-Chief's Message
Micro Economics
Features
- Sarita V. Adve, Pia Sanda:
Guest Editors' Introduction: Reliability-Aware Microarchitecture.
8-9
Electronic Edition (link) BibTeX
- Shekhar Y. Borkar:
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation.
10-16
Electronic Edition (link) BibTeX
- Ravishankar K. Iyer, Nithin Nakka, Zbigniew Kalbarczyk, Subhasish Mitra:
Recent Advances and New Avenues in Hardware-Level Reliability Support.
18-29
Electronic Edition (link) BibTeX
- Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer:
An Experimental Study of Soft Errors in Microprocessors.
30-39
Electronic Edition (link) BibTeX
- Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron:
Improved Thermal Management with Reliability Banking.
40-49
Electronic Edition (link) BibTeX
- Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
TRUSS: A Reliable, Scalable Server Architecture.
51-59
Electronic Edition (link) BibTeX
- M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi:
Power-Efficient Error Tolerance in Chip Multiprocessors.
60-70
Electronic Edition (link) BibTeX
- Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang:
Cell Processor Low-Power Design Methodology.
71-78
Electronic Edition (link) BibTeX
Micro Innovations
Micro Review
Micro Law
Copyright © Sun May 17 00:13:22 2009
by Michael Ley (ley@uni-trier.de)
