2003 |
9 | EE | Cindy Eisner,
Dana Fisman,
John Havlicek,
Yoad Lustig,
Anthony McIsaac,
David Van Campenhout:
Reasoning with Temporal Logic on Truncated Paths.
CAV 2003: 27-39 |
8 | EE | Cindy Eisner,
Dana Fisman,
John Havlicek,
Anthony McIsaac,
David Van Campenhout:
The Definition of a Temporal Clock Operator.
ICALP 2003: 857-870 |
2000 |
7 | EE | David Van Campenhout,
Trevor N. Mudge,
John P. Hayes:
Collection and Analysis of Microprocessor Design Errors.
IEEE Design & Test of Computers 17(4): 51-60 (2000) |
1999 |
6 | EE | David Van Campenhout,
Trevor N. Mudge,
John P. Hayes:
High-Level Test Generation for Design Verification of Pipelined Microprocessors.
DAC 1999: 185-188 |
5 | EE | David Van Campenhout,
Trevor N. Mudge,
Karem A. Sakallah:
Timing verification of sequential dynamic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 645-658 (1999) |
1998 |
4 | EE | James K. Huggins,
David Van Campenhout:
Specification and verification of pipelining in the ARM2 RISC microprocessor.
ACM Trans. Design Autom. Electr. Syst. 3(4): 563-580 (1998) |
3 | EE | David Van Campenhout,
Hussain Al-Asaad,
John P. Hayes,
Trevor N. Mudge,
Richard B. Brown:
High-level design verification of microprocessors via error modeling.
ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998) |
1996 |
2 | EE | David Van Campenhout,
Trevor N. Mudge,
Karem A. Sakallah:
Timing verification of sequential domino circuits.
ICCAD 1996: 127-132 |
1993 |
1 | | Dirk Daneels,
David Van Campenhout,
Wayne Niblack,
William Equitz,
Ron Barber,
Erwin Bellon,
Freddy Fierens:
Interactive Outlining: An Improved Approach Using Active Contours.
Storage and Retrieval for Image and Video Databases (SPIE) 1993: 226-233 |