| |
| 2006 | ||
|---|---|---|
| 2 | EE | Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein: From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4 |
| 1 | Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein: Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC 2006: 46-51 | |
| 1 | Jürgen Becker | [1] [2] |
| 2 | Reiner W. Hartenstein | [1] [2] |
| 3 | Carlos Morra | [1] [2] |
| 4 | Sunil Shukla | [2] |