ARC 2008: London, UK

Roger F. Woods, Katherine Compton, Christos-Savvas Bouganis, Pedro C. Diniz (Eds.): Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings. Lecture Notes in Computer Science 4943 Springer 2008, ISBN 978-3-540-78609-2 BibTeX

Keynotes

Satnam Singh, David J. Greaves:
Synthesizing FPGA Circuits from Parallel Programs. 1
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Keith D. Underwood:
From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing. 2
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Reiner Hartenstein:
The von Neumann Syndrome and the CS Education Dilemma. 3
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Programming and Compilation

Ozana Silvia Dragomir, Elena Moscu Panainte, Koen Bertels, Stephan Wong:
Optimal Unroll Factor for Reconfigurable Architectures. 4-14
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Samar Yazdani, Joel Cambonie, Bernard Pottier:
Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems. 15-26
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DNA and String Processing Applications

Adriano Idalgo, Nahri Moreano:
DNA Physical Mapping on a Reconfigurable Platform. 27-38
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Fei Xia, Yong Dou, Jinbo Xu:
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension. 39-50
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Chia-Tien Dan Lo, Yi-Gang Tai:
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs. 51-62
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Scientific Applications

Filipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José C. Alves:
A Custom Processor for a TDMA Solver in a CFD Application. 63-74
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Antonio Roldao Lopes, George A. Constantinides:
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. 75-86
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Reconfigurable Computing Hardware and Systems

Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. 87-98
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Shane Santner, Wesley Peck, Jason Agron, David L. Andrews:
Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. 99-110
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Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro:
Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. 111-123
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Image Processing

Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. 124-135
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Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Parallel Hardware Architecture for Image Feature Detection. 136-147
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Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele:
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. 148-158
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Run-Time Behavior

Slavisa Jovanovic, Camel Tanougast, Serge Weber:
A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems. 159-170
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Vu Manh Tuan, Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. 171-182
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Hagen Gädke, Andreas Koch:
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens. 183-194
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Instruction Set Extension

Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis:
ARISE Machines: Extending Processors with Hybrid Accelerators. 195-206
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Carlo Galuzzi, Koen Bertels:
The Instruction-Set Extension Problem: A Survey. 207-218
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Random Number Generation and Financial Computation

Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk:
An FPGA run-time parameterisable Log-Normal Random Number Generator. 219-230
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Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. 231-242
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Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. 243-253
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Posters

Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong:
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. 254-259
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Vítor Silva, Rui Duarte, Mário P. Véstias, Horácio C. Neto:
Multiplier-based double precision floating point divider according to the IEEE-754 standard. 260-265
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Haruna Cofer, Matthias Fouquet-Lapar, Timothy Gamerdinger, Christopher Lindahl, Bruce Losure, Alan Mayer, James Swoboda, Teruo Utsumi:
Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable ALTIX System Infrastructure and Benchmarking Life-Science Applications. 266-271
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Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr:
Highly efficient structure of 64-bit exponential function implemented in FPGAs. 272-277
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Carlo Galuzzi, Koen Bertels:
A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures. 278-283
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Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich:
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. 284-289
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Piotr Dziurzanski, Tomasz Maka:
Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on Chip. 290-295
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Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek:
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. 296-301
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Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. 302-307
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Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker:
Data reallocation by exploiting FPGA configuration mechanisms. 308-313
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Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet:
A Networked, Lightweight and Partially Reconfigurable Platform. 314-319
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Yo-Hsien Lin, Jong-Chen Chen:
Neuromolecularware -- A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis. 320-325
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Masaki Nakanishi:
An FPGA Configuration Scheme for Bitstream Protection. 326-331
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Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez:
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. 332-337
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