ARC 2009:
Karlsruhe,
Germany
Jürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan (Eds.):
Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings.
Lecture Notes in Computer Science 5453 Springer 2009, ISBN 978-3-642-00640-1 BibTeX
Keynotes
Applications 1
Applications 2
FPGA Security and Bitstream Analysis
Fault Tolerant Systems
Architectures
Place and Route Techniques
- Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung:
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep.
133-144
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- Ricardo Ferreira, Alex Damiany, Julio Vendramini, Tiago Teixeira, João M. P. Cardoso:
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.
145-156
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- Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini:
A New Datapath Merging Method for Reconfigurable System.
157-168
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Cryptography
Resource Allocation and Scheduling
Applications 3
Posters
- José Manuel Moya, Javier Rodríguez, Julio Martín, Juan Carlos Vallejo, Pedro Malagón, Álvaro Araujo, Juan-Mariano de Goyeneche, Agustín Rubio, Elena Romero, Daniel Villanueva, Octavio Nieto-Taladriz, Carlos A. López-Barrio:
SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems.
255-260
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- Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura:
A Parallel Branching Program Machine for Emulation of Sequential Circuits.
261-267
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- Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
Memory Sharing Approach for TMR Softcore Processor.
268-274
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- Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin:
The Need for Reconfigurable Routers in Networks-on-Chip.
275-280
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- Fernando Rincón, Jesús Barba, Francisco Moya, Juan Carlos López, Julio Dondo:
Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware.
281-286
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- Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan:
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder.
287-292
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- Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Morisothi Yasunaga:
Tile-Based Fault Tolerant Approach Using Partial Reconfiguration.
293-299
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- SangKyun Yun, KyuHee Lee:
Regular Expression Pattern Matching Supporting Constrained Repetitions.
300-305
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- Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr:
Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function.
306-311
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- Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga:
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications.
312-317
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- Dimitris Theodoropoulos, Alexandros Siskos, Dionisis Pnevmatikatos:
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers.
318-323
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- Sirisak Leephokhanon, Theerayod Wiangtong:
Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System.
324-329
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- Raphael Weber, Achim Rettberg:
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.
330-335
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- Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire:
A Hardware Accelerated Simulation Environment for Spiking Neural Networks.
336-341
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- Yahya Jan, Lech Józwiak:
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.
342-348
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- Beniamin Apopei, Andy Mills, Tony Dodd, Haydn Thompson:
Real Time Simulation in Floating Point Precision Using FPGA Computing.
349-354
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- Brian Baldwin, Richard Moloney, Andrew Byrne, Gary McGuire, William P. Marnane:
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem.
355-361
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- Rainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl:
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems.
362-367
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- Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri:
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.
368-373
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- Andreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick:
ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach.
374-379
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- Markus Happe, Enno Lübbers, Marco Platzner:
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.
380-385
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Copyright © Sat May 16 22:58:25 2009
by Michael Ley (ley@uni-trier.de)
