| 2006 |
|---|
| 6 | EE | Carsten Bieser:
A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment.
FPL 2006: 1-2 |
| 5 | EE | Carsten Bieser,
Martin Bahlinger,
Matthias Heinz,
Christian Stops,
Klaus D. Müller-Glaser:
A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup.
FPL 2006: 1-4 |
| 4 | EE | Carsten Bieser,
Klaus D. Müller-Glaser:
Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs.
IEEE International Workshop on Rapid System Prototyping 2006: 193-199 |
| 2005 |
|---|
| 3 | EE | Carsten Bieser,
Klaus D. Müller-Glaser:
COMPASS - A Novel Concept of a Reconfigurable Platform for Automotive System Development and Test.
IEEE International Workshop on Rapid System Prototyping 2005: 135-140 |
| 2 | EE | Carsten Bieser,
Klaus D. Müller-Glaser,
Jürgen Becker:
Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling.
MSE 2005: 51-52 |
| 2003 |
|---|
| 1 | EE | Jens E. Becker,
Carsten Bieser,
Alexander Thomas,
Klaus D. Müller-Glaser,
Jürgen Becker:
Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core.
MSE 2003: 134-135 |
