16. FCCM 2008:
Stanford,
Palo Alto,
USA
Kenneth L. Pocek, Duncan A. Buell (Eds.):
16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA.
IEEE Computer Society 2008, ISBN 978-0-7695-3307-0 BibTeX
Programming
Network Applications
Reconfiguration
Discrete Applications
Compilation
- William G. Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer:
Power-Aware and Branch-Aware Word-Length Optimization.
129-138
Electronic Edition (link) BibTeX
- Kenneth Eguro, Scott Hauck:
Simultaneous Retiming and Placement for Pipelined Netlists.
139-148
Electronic Edition (link) BibTeX
- Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, Bill S. H. Kwan, Chris C. C. Cheung, Anthony P. C. Chan, Philip Heng Wai Leong:
Map-reduce as a Programming Model for Custom Computing Machines.
149-159
Electronic Edition (link) BibTeX
Image Processing
Processor-Based Architectures
High-Performance Computing
Posters
- Sven-Ole Voigt, Thomas Teufel:
Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms.
261-262
Electronic Edition (link) BibTeX
- Tian Hangpei, Deyuan Gao, Wei Wu, Xiaoya Fan, Zhu Yian:
Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion.
263-264
Electronic Edition (link) BibTeX
- Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan:
ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.
265-268
Electronic Edition (link) BibTeX
- Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman:
An Extensible I/O Subsystem.
269-270
Electronic Edition (link) BibTeX
- Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi:
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding.
271-272
Electronic Edition (link) BibTeX
- Georgios-Grigorios Mplemenos, Ioannis Papaefstathiou:
MPLEM: An 80-processor FPGA Based Multiprocessor System.
273-274
Electronic Edition (link) BibTeX
- Hanyu Liu, Xiaolei Chen, Yajun Ha:
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects.
275-276
Electronic Edition (link) BibTeX
- Emilio Castillo, Cesar Pedraza, Javier Castillo, Cristobal Camarero, José Luis Bosque, Rafael Menéndez de Llano, José I. Martínez:
SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable Hardware.
277-278
Electronic Edition (link) BibTeX
- Miad Faezipour, Mehrdad Nourani:
Reconfigurable Constraint Repetition Unit for Regular Expression Matching.
279-280
Electronic Edition (link) BibTeX
- Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter:
Fast Multivariate Signature Generation in Hardware: The Case of Rainbow.
281-282
Electronic Edition (link) BibTeX
- Andrew J. Wong, Warren J. Gross:
Configurable Flow Models for FPGA Particle Graphics Engines.
283-284
Electronic Edition (link) BibTeX
- Hayden Kwok-Hay So, Robert W. Brodersen:
Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH.
285-286
Electronic Edition (link) BibTeX
- Dirk Koch, Christian Haubelt, Jürgen Teich:
Efficient Reconfigurable On-Chip Buses for FPGAs.
287-290
Electronic Edition (link) BibTeX
- Andrew W. H. House, Paul Chow:
Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems.
291-292
Electronic Edition (link) BibTeX
- Karl Meier, Alessandro Forin:
Hardware Compilation from Machine Code with M2V.
293-295
Electronic Edition (link) BibTeX
- David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor, Steve Poole:
An Implementation of the Conjugate Gradient Algorithm on FPGAs.
296-297
Electronic Edition (link) BibTeX
- Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass:
FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs.
298-299
Electronic Edition (link) BibTeX
- Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass:
Reconfigurable Computing Cluster Project: Phase I Brief.
300-301
Electronic Edition (link) BibTeX
- Karthik Nagarajan, Brian Holland, K. Clint Slatton, Alan D. George:
Scalable and Portable Architecture for Probability Density Function Estimation on FPGAs.
302-303
Electronic Edition (link) BibTeX
- Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen:
A Hardware Efficient Support Vector Machine Architecture for FPGA.
304-305
Electronic Edition (link) BibTeX
- Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.
306-309
Electronic Edition (link) BibTeX
- Ling Zhuo, Qingbo Wang, Viktor K. Prasanna:
Matrix Computations on Heterogeneous Reconfigurable Systems.
310-311
Electronic Edition (link) BibTeX
- Jason Wu, John W. Williams, Neil Bergmann:
System Level Design Methodology for Hybrid Multi-Processor SoC on FPGA.
312-313
Electronic Edition (link) BibTeX
- François Charot, Christophe Wolinski, Nicolas Fau, François Hamon:
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture.
314-315
Electronic Edition (link) BibTeX
- Sherman Braganza, Miriam Leeser:
An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware.
316-317
Electronic Edition (link) BibTeX
- Edward Chen, William A. Gruver, Dorian Sabaz, Lesley Shannon:
Facilitating Processor-Based DPR Systems for non-DPR Experts.
318-319
Electronic Edition (link) BibTeX
- Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker:
Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.
320-321
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:11:55 2009
by Michael Ley (ley@uni-trier.de)
