ASAP 1995:
Strasbourg,
France
The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France.
IEEE Computer Society 1995 BibTeX
@proceedings{DBLP:conf/asap/1995,
title = {The International Conference on Application Specific Array Processors
(ASAP'95), July 24-26, 1995, Strasbourg, France},
publisher = {IEEE Computer Society},
year = {1995},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Scheduling and Mapping
Architectures I
- Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing, Larry Wilson:
Time-optimal ranking algorithms on sorted matrices.
42-53
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- Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri:
Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks.
54-65
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- Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee:
Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor.
66-75
Electronic Edition (link) BibTeX
- Anders Kugler, Roger D. Hersch:
A Scalable Halftoning Coprocessor Architecture.
76-84
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- Paolo Ienne:
Horizontal Microcode Compaction for Programmable Systolic Accelerators.
85-
Electronic Edition (link) BibTeX
Arithmetic I
Poster Presentations
- Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin:
The MGAP's programming environment and the *C++ language.
121-124
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- B. Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis:
The VLSI design and implementation of the array processors of a multilayer vision system architecture.
125-128
Electronic Edition (link) BibTeX
- Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine.
129-132
Electronic Edition (link) BibTeX
- Amar Mukherjee, Tinku Acharya:
VLSI Algorithms for Compressed Pattern Search Using Tree Based Codes.
133-136
Electronic Edition (link) BibTeX
- Richard Hughey:
Parallel Sequence Comparison and Alignment.
137-140
Electronic Edition (link) BibTeX
- D. W. Brown, F. M. F. Gaston:
The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs.
141-
Electronic Edition (link) BibTeX
Signal and Image Processing
Motion Estimation
- Pierpaolo Baglietto, Massimo Maresca, A. Migliaro, Mauro Migliardi:
Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation.
182-192
Electronic Edition (link) BibTeX
- Ronan Barzic, Christian Bouville, François Charot, Gwendal Le Fol, Pascal Lemonnier, Charles Wagner:
MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms.
193-203
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- Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens:
Motion Estimation Algorithms on Fine Grain Array Processor.
204-213
Electronic Edition (link) BibTeX
- Yin Chan, Sun-Yuan Kung:
Bit Level Block Matching Systolic Arrays.
214-
Electronic Edition (link) BibTeX
Architecture II
Arithmetic II
- Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Digit On-line Large Radix CORDIC Rotator.
246-257
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- Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
CORDIC Architectures with Parallel Compensation of the Scale Factor.
258-269
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- Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, William C. Miller, Zhongde Wang:
An array processor for inner product computations using a Fermat number ALU.
270-281
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- Tudor Jebelean:
Design of a systolic coprocessor for rational addition.
282-289
Electronic Edition (link) BibTeX
- Valentina P. Markova:
Multilayer Cellular Algorithm for Complex Number Multiplication.
290-
Electronic Edition (link) BibTeX
Design Methodologies
Copyright © Sat May 16 22:58:34 2009
by Michael Ley (ley@uni-trier.de)
