Zdenek Kotásek

2008
19	EE	Lukás Starecek, Lukás Sekanina, Zdenek Kotásek: Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS 2008: 255-268
18	EE	Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek: Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
17	EE	Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Testability analysis based on the identification of testable blocks with predefined properties. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 296-302 (2008)
2007
16	EE	Martin Straka, Jiri Tobola, Zdenek Kotásek: Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT 2007: 152-160
15	EE	Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD 2007: 611-618
14	EE	Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka: Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD 2007: 676-679
2006
13		Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 IEEE Computer Society 2006
12	EE	Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek: Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS 2006: 186-193
11		Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina: FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS 2006: 285-289
10		Lukás Sekanina, Lukás Starecek, Zdenek Kotásek: Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS 2006: 85-86
9	EE	Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina: Testability Estimation Based on Controllability and Observability Parameters. DSD 2006: 504-514
8	EE	Josef Strnadel, Zdenek Kotásek: SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS 2006: 497-498
2005
7	EE	Josef Strnadel, Zdenek Kotásek: Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD 2005: 420-427
6	EE	Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel: Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware 2005: 51-58
2003
5	EE	Zdenek Kotásek, Daniel Mika, Josef Strnadel: Test scheduling for embedded systems. DSD 2003: 463-467
2002
4	EE	Josef Strnadel, Zdenek Kotásek: Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD 2002: 166-173
1997
3	EE	Zdenek Kotásek, F. Zboril: RT level testability analysis to reduce test application time. EUROMICRO 1997: 104-
2		J. Blatný, Zdenek Kotásek, Jan Hlavicka: RT Level Test Scheduling. Computers and Artificial Intelligence 16(1): (1997)
1995
1		J. Blatný, Zdenek Kotásek: I-Path Analysis. Computers and Artificial Intelligence 14(5): (1995)

Coauthor Index

1	J. Blatný	[1] [2]
2	Jiri Bucek	[13]
3	Zbysek Gajda	[12]
4	Tomas Herrman	[15] [17]
5	Jan Hlavicka	[2]
6	Jan Korenek	[14]
7	Pavel Kubalík	[13]
8	Hana Kubatova	[13]
9	Tomás Martínek	[14]
10	Daniel Mika	[5]
11	Ondrej Novák	[13]
12	Tomas Pecenka	[6] [9] [11] [18]
13	Matteo Sonza Reorda	[13]
14	Lukás Sekanina	[6] [9] [10] [11] [12] [18] [19]
15	Jaroslav Skarvada	[15] [17]
16	Lukás Starecek	[10] [12] [19]
17	Martin Straka	[14] [16]
18	Bernd Straube	[13]
19	Josef Strnadel	[4] [5] [6] [7] [8] [9]
20	Jiri Tobola	[14] [16]
21	Raimund Ubar	[13]
22	F. Zboril	[3]

Colors in the list of coauthors