| 2007 |
|---|
| 10 | | Sindhu Kakarla,
Waleed Al-Assadi:
Scan-Based Detection of Crosstalk Noise in FPGAs.
CDES 2007: 121-126 |
| 9 | | Mandar Joshi,
Waleed Al-Assadi:
Nanofabric PLA Architecture with Double Variable Redundancy.
CDES 2007: 17-21 |
| 8 | | Vipin Sharma,
Waleed Al-Assadi,
Ashwin Vasudevan:
A Built-in Current Monitor Design for Transient Current Testing.
CDES 2007: 44-46 |
| 7 | EE | Waleed Al-Assadi,
Sindhu Kakarla:
Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design.
DFT 2007: 215-222 |
| 6 | EE | Mandar V. Joshi,
Waleed Al-Assadi:
Nanofabric PLA architecture with Redundancy Enhancement.
DFT 2007: 427-435 |
| 5 | EE | Venkat Satagopan,
Bonita Bhaskaran,
Waleed Al-Assadi,
Scott C. Smith,
Sindhu Kakarla:
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.
IEEE Trans. VLSI Syst. 15(10): 1155-1159 (2007) |
| 2006 |
|---|
| 4 | | Waleed Al-Assadi,
Vipin Sharma,
Pavankumar Chandrasekhar:
Crosstalk at the Dynamic Node of Domino CMOS Circuits.
CDES 2006: 57-63 |
| 2005 |
|---|
| 3 | | Waleed Al-Assadi,
Thomas Dick:
Design for Test Methodology for the IBM PowerPC 440 Embedded Core.
CDES 2005: 109-114 |
| 2 | | Waleed Al-Assadi,
Pavankumar Chandrasekhar,
Bonita Bhaskaran:
Fault Modeling and Testability of CMOS Domino Circuits.
CDES 2005: 21-27 |
| 1 | | Bonita Bhaskaran,
Venkat Satagopan,
Waleed Al-Assadi,
Scott C. Smith:
Implementation of Design For Test for Asynchronous NCL Designs.
CDES 2005: 78-84 |
