| 2009 |
|---|
| 9 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Axel Poschmann,
Johann Großschädl,
Frank K. Gürkaynak,
Marco Macchetti,
Zeynep Toprak Deniz,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Transactions on Computational Science 4: 230-243 (2009) |
| 2008 |
|---|
| 8 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Luca Breveglieri,
Paolo Ienne,
Israel Koren:
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.
DFT 2008: 202-210 |
| 2007 |
|---|
| 7 | EE | André C. Nácul,
Francesco Regazzoni,
Marcello Lajolo:
Hardware scheduling support in SMP architectures.
DATE 2007: 642-647 |
| 6 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Johann Großschädl,
Luca Breveglieri,
Paolo Ienne,
Israel Koren,
Christof Paar:
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
DFT 2007: 508-516 |
| 5 | EE | Francesco Regazzoni,
Stéphane Badel,
Thomas Eisenbarth,
Johann Großschädl,
Axel Poschmann,
Zeynep Toprak Deniz,
Marco Macchetti,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS 2007: 209-214 |
| 4 | EE | Matteo Giaconia,
Marco Macchetti,
Francesco Regazzoni,
Kai Schramm:
Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes.
VLSI Design 2007: 731-737 |
| 2006 |
|---|
| 3 | EE | Sathish Chandra,
Francesco Regazzoni,
Marcello Lajolo:
Hardware/software partitioning of operating systems: a behavioral synthesis approach.
ACM Great Lakes Symposium on VLSI 2006: 324-329 |
| 2 | EE | Guido Bertoni,
Luca Breveglieri,
Farina Roberto,
Francesco Regazzoni:
Speeding Up AES By Extending a 32 bit Processor Instruction Set.
ASAP 2006: 275-282 |
| 2005 |
|---|
| 1 | EE | Francesco Regazzoni,
André C. Nácul,
Marcello Lajolo:
Automatic synthesis of the Hardware/Software Interface.
FDL 2005: 401-405 |
