| |
| 1999 | ||
|---|---|---|
| 2 | EE | Chun-hong Chen, Chi-Ying Tsui: Timing Optimization of Logic Network Using Gate Duplication. ASP-DAC 1999: 233-236 |
| 1998 | ||
| 1 | EE | Chun-hong Chen, Chi-Ying Tsui: Towards the capability of providing power-area-delay trade-off at the register transfer level. ISLPED 1998: 24-29 |
| 1 | Chi-Ying Tsui | [1] [2] |