| 2002 |
|---|
| 5 | EE | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau,
Ren-Der Chen:
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. VLSI Syst. 10(6): 924-929 (2002) |
| 2001 |
|---|
| 4 | EE | Jer-Min Jou,
Yeu-Horng Shiau,
Chin-Chi Liu:
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme.
ISCAS (2) 2001: 529-532 |
| 1999 |
|---|
| 3 | EE | Ren-Der Chen,
Jer-Min Jou,
Yeu-Horng Shiau:
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.
ASP-DAC 1999: 185-188 |
| 2 | EE | Jer-Min Jou,
Pei-Yin Chen,
Yeu-Horng Shiau,
Ming-Shiang Liang:
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.
ASP-DAC 1999: 205-208 |
| 1 | EE | Jer-Min Jou,
Shiann-Rong Kuang,
Yeu-Horng Shiau:
A New Pipelined Architecture for Fuzzy Color Correction.
ASP-DAC 1999: 209- |
