| |
| 2002 | ||
|---|---|---|
| 4 | EE | Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen: Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. VLSI Syst. 10(6): 924-929 (2002) |
| 1999 | ||
| 3 | EE | Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau: Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC 1999: 185-188 |
| 1994 | ||
| 2 | Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang: Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. ISCAS 1994: 45-48 | |
| 1 | Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen: A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. ISCAS 1994: 85-88 | |
| 1 | Shung-Chih Chen | [1] |
| 2 | Jer-Min Jou | [1] [2] [3] [4] |
| 3 | Shiann-Rong Kuang | [2] [4] |
| 4 | Yeu-Horng Shiau | [3] [4] |